参数资料
型号: ISL6263CRZ
厂商: Intersil
文件页数: 17/19页
文件大小: 0K
描述: IC VREG CORE 5BIT 1PHASE 32-QFN
标准包装: 60
应用: 转换器,Intel IMVP-6
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.41 V ~ 1.29 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6263
actual board by examining the transient voltage. It is
recommended to choose the minimum capacitance based
on the maximum inductance. C N also needs to be a high-
grade capacitor such as NPO/COG or X7R with tight
tolerance. The NPO/COG caps are only available in small
capacitance values. In order to use such capacitors, the
resistors and thermistors surrounding the droop voltage
sensing and droop amplifier need to be scaled up 10x to
reduce the capacitance by 10x.
Static and Dynamic Droop using Discrete Resistor
Sensing
Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 9 shows the
equivalent circuit. Since the current sensing resistor voltage
represents the actual inductor current information, R S and
C N simply provide noise filtering. A low ESL sensing resistor
is strongly recommended for R SNS because this parameter
is the most significant source of noise that affects discrete
resistor sensing. It is recommended to start out using 100 Ω
for R S and 47pF for C N . Since the current sensing
resistance changes very little with temperature, the NTC
network is not needed for thermal compensation. Discrete
resistor sensing droop design follows the same approach as
DCR sensing. The voltage on the current sensing resistor is
given by Equation 20:
calculate the compensator parameters. Caution needs to be
used in choosing the input resistor to the FB pin. Excessively
high resistance will cause an error to the output voltage
regulation due to the bias current flowing through the FB pin.
It is recommended to keep this resistor below 3k Ω .
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding.
Inductor Current Sensing and the NTC Placement
It is crucial that the inductor current be sensed directly at the
PCB pads of the sense element, be it DCR sensed or
discrete resistor sensed. The effect of the NTC on the
inductor DCR thermal drift is directly proportional to its
thermal coupling with the inductor and thus, the physical
proximity to it.
Signal Ground and Power Ground
The ground plane layer should have a single point
connection to the analog ground at the VSS pin. The VSS
island should be located under the IC package along with
the weak analog traces and components. The paddle on the
bottom of the ISL6263 QFN package is not electrically
V RSNS = I o ? R SNS
(EQ. 20)
connected to the IC however, it is recommended to make a
good thermal connection to the VSS island using several
Equation 21 shows the droop amplifier gain. So the actual
droop is given by:
vias. Connect the input capacitors, the output capacitors,
and the source of the lower MOSFETs to the power ground
plane.
R droop = R SNS ? ? 1 + ------------------- ?
R DRP2 = R DRP1 ? ? ?
? R droop ?
? R SNS
? R DRP2 ?
? R DRP1 ?
Solution to R DRP2 yields Equation 22:
------------------- – 1
?
(EQ. 21)
(EQ. 22)
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace
should be routed in parallel with the trace from the PGND
For example: R droop = 8.0m Ω , R SNS = 1.0m Ω , and
R DRP1 = 1k Ω , R DRP2 then = 7k Ω.
The current sensing traces should be routed directly to the
current sensing resistor pads for accurate measurement.
pin. These two traces should be short, wide, and away from
other traces because of the high peak current and extremely
fast dv/dt. PVCC should be decoupled to PGND with a
ceramic capacitor physically located as close as practical to
the IC pins.
However, due to layout imperfection, the calculated R DRP2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R DRP2 after the system
has achieved thermal equilibrium at full load.
VIAS TO
GROUND
PLANE
GND
VOUT
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
INDUCTOR
MOSFETS
Dynamic Mode of Operation - Compensation
Parameters
The voltage regulator is equivalent to a voltage source in
series with the output impedance. The voltage source is the
VID state and the output impedance is 8.0m Ω in order to
achieve the 8.0mV/A load line. It is highly recommended to
design the compensation such that the regulator output
impedance is 8.0m Ω . Intersil provides a spreadsheet to
17
PHASE
NODE
HIGH-SIDE
MOSFETS INPUT
VIN CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
FN9213.2
June 10, 2010
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ISL6263DHRZ 功能描述:IC VREG 3BIT 1PHASE 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源,ICERA E400,E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA,WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR)
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