参数资料
| 型号： | ISL6263CRZ |
| 厂商： | Intersil |
| 文件页数： | 8/19页 |
| 文件大小： | 0K |
| 描述： | IC VREG CORE 5BIT 1PHASE 32-QFN |
| 标准包装： | 60 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.41 V ~ 1.29 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 管件 |
ISL6263
Electrical Specifications
These specifications apply for T A = -10°C to +100°C, unless otherwise stated. All typical specifications
T A = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C. (Continued)
MIN
MAX
PARAMETER
VR_ON Input High
AF_EN Input Low
AF_EN Input High
VR_ON Leakage
AF_EN Leakage
VID<4:0> Input Low
VID<4:0> Input High
FDE Input Low
FDE Input High
VID<4:0> Leakage
FDE Leakage
SYMBOL
V VR_ONH
V AF_ENL
V AF_ENH
I VR_ONL
I VR_ONH
I AF_ENL
I AF_ENH
V VIDL
V VIDH
V FDEL
V FDEH
I VIDL
I VIDH
I FDEL
I FDEH
TEST CONDITIONS
V VR_ON = 0V
V VR_ON = 3.3V
V AF_EN = 0V
V AF_EN = 3.3V
V VID = 0V
V VID = 1.0V
V FDE = 0V
V FDE = 1.0V
(Note 6)
2.3
-
2.3
-1.0
-
-1.0
-
-
0.7
-
0.7
-1.0
-
-1.0
-
TYP
-
-
-
0
0
0
0.45
-
-
-
-
0
0.45
0
0.45
(Note 6)
-
1
-
-
1.0
-
1.0
0.3
-
0.3
-
-
1.0
-
1.0
UNITS
V
V
V
μA
μA
μA
μA
V
V
V
V
μA
μA
μA
μA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
8. Limits should be considered typical and are not production tested.
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10μ A current reference.
Connect a 150k Ω ±1 % resistor from RBIAS to VSS.
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
an X5R or X7R ceramic capacitor from SOFT to VSS. The
SOFT pin is the non-inverting input of the error amplifier.
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
resistor from OCSET to VO.
VW (Pin 4) - Sets the static PWM switching frequency in
continuous conduction mode. Connect a resistor from VW to
COMP.
COMP (Pin 5) - Connects to the output of the control loop
error amplifier.
FB (Pin 6) - Connects to the inverting input of the control
loop error amplifier.
VDIFF (Pin 7) - Connects to the output of the VDIFF
differential-summing amplifier.
VSEN (Pin 8) - This is the V CC_SNS input of the processor
socket Kelvin connection. Connects internally to one of two
non-inverting inputs of the VDIFF differential-summing
amplifier.
8
RTN (Pin 9) - This is the V SS_SNS input of the processor
socket Kelvin connection. Connects internally to one of two
inverting inputs of the VDIFF differential-summing amplifier.
DROOP (Pin 10) - Connects to the output of the droop
differential amplifier and to one of two non-inverting inputs of
the VDIFF differential-summing amplifier.
DFB (Pin 11) - This is the feedback of the droop amplifier.
Connects internally to the inverting input of the droop
differential amplifier.
VO (Pin 12) - Connects to one of two inverting inputs of the
VDIFF differential-summing amplifier.
VSUM (Pin 13) - Connects to the non-inverting input of the
droop differential amplifier.
VIN (Pin 14) - Connects to the R 3 PWM modulator providing
input voltage feed-forward. For optimum input voltage
transient response, connect near the drain of the high-side
MOSFETs.
VSS (Pin 15) - Analog ground.
VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1μF MLCC capacitor
from the VDD pin to the VSS pin.
FN9213.2
June 10, 2010
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