参数资料
| 型号： | ISL6265AHRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/23页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48-TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
ISL6265A
an error amplifier that allows the controller to maintain a
0.5% voltage regulation accuracy throughout the VID range
from 0.75V to 1.55V. Voltage regulation accuracy is slightly
wider, ±5mV, over the VID range from 0.7375V to 0.5V.
and SVD pins to determine the soft-start target output
voltage level. .
VIN
The hysteresis window voltage is relative to the error
PWM FREQUENCY
CONTROL
FSET
amplifier output such that load current transients result in
increased switching frequency, which gives the R 3 regulator
a faster response than conventional fixed frequency PWM
controllers. In uniplane configurations, transient load current
is inherently shared between active phases due to the use of
a common hysteretic window voltage. Individual average
phase currents are monitored and controlled to equally
share current among the active phases.
VO
+
g m V IN
+
g m V O
+
-
+
V W
-
V R
V COMP
C R TO
PWM
CONTROL
+
+
R
PWM Q
S
ISL6265A
Modulator
The ISL6265A modulator features Intersil’s R 3 technology, a
hybrid of fixed frequency PWM control and variable frequency
hysteretic control (see Figure 5). Intersil’s R 3 technology can
FIGURE 5. MODULATOR CIRCUITRY
simultaneously affect the PWM switching frequency and PWM
duty cycle in response to input voltage and output load
transients. The R 3 modulator synthesizes an AC signal V R ,
which is an analog representation of the output inductor ripple
current. The duty-cycle of V R is the result of charge and
discharge current through a ripple capacitor C R . The current
RIPPLE CAPACITOR VOLTAGE C R
WINDOW VOLTAGE V W
through C R is provided by a transconductance amplifier g m
that measures the VIN and VO voltages. The positive slope of
ERROR AMPLIFIER VOLTAGE V COMP
V R can be written as determined by Equation 1:
V RPOS = ( g m ) ? ( V IN – V OUT )
(EQ. 1)
The negative slope of V R can be written as determined by
Equation 2:
PWM
V RNEG = g m ? V OUT
(EQ. 2)
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
Where g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V W is the higher threshold voltage. Figure 6 shows
PWM pulses being generated as V R traverses the V W and
V COMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V R; it is inversely proportional to the voltage
between V W and V COMP .
Initialization
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
operation profile prior to ENABLE. These pins include RTN1
which determines single vs two-phase operation and
OFS/VFIXEN for enabling/disabling the SVI interface and
core voltage droop. Depending on the configuration set by
these pins, the controller then checks the state of the SVC
11
TRANSIENT
Power-On Reset
The ISL6265A requires a +5V input supply tied to VCC and
PVCC to exceed a rising power-on reset (POR) threshold
before the controller has sufficient bias to guarantee proper
operation. Once this threshold is reached or exceeded, the
ISL6265A has enough bias to begin checking RTN1,
OFS/VFIXEN, ENABLE, and SVI inputs. Hysteresis between
the rising the falling thresholds assure the ISL6265A will not
inadvertently turn-off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 8).
Core Configuration
The ISL6265A determines the core channel requirements of
the CPU based on the state of the RTN1 pin prior to ENABLE. If
RTN1 is low prior to ENABLE, both VDD0 and VDD1 core
planes are required. The core controllers operate as
independent single-phase regulators. RTN1 is connected to the
CPU Core1 negative sense point. For single core CPU designs
(uniplane), RTN1 is tied to a +1.8V or greater supply. Prior to
ENABLE, RTN1 is detected as HIGH and the ISL6265A drives
the core controllers as a two-phase multi-phase regulator. Dual
purpose motherboard designs should include resistor options to
FN6884.0
May 11, 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6265C | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs |
| ISL6265C_10 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs |
| ISL6265CEVAL1Z | 制造商:Intersil Corporation 功能描述:ISL6265 EVALUATION BOARD 1 - 48 LD TQFN - ROHS COMPLIANT - Bulk |
| ISL6265CHRTZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265CHRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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