参数资料
型号: ISL6265AHRTZ-T
厂商: Intersil
文件页数: 8/23页
文件大小: 0K
描述: IC CTRLR MULTI-OUTPUT 48-TQFN
标准包装: 4,000
应用: 控制器,AMD SVI 兼容移动式 CPU
输入电压: 5 V ~ 24 V
输出数: 3
输出电压: 0.5 V ~ 1.55 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
ISL6265A
Electrical Specifications
VCC = PVCC = 5V, V IN = 12V, T A = -10°C to +100°C, Unless Otherwise Specified. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFFSET FUNCTION
OFS Pin Voltage For Droop Enabling
FB Pin Source Current
OFS Pin Voltage Threshold for VFIX
V OFS
I FB
V OFS
R OFS = 240k Ω (OFS pin to GND)
I OFS = 10μA
1.18
9.0
-
1.2
9.9
1.8
1.22
10.8
-
V
μA
V
Mode and No Droop Operation
OFS Pin Voltage Threshold for SVI
V OFS
-
4.0
-
V
Mode and No Droop Operation
OFS Bias
I OFS
1.8V < OFS < VCC
-
4.0
-
μA
LOGIC INPUTS
ENABLE Low Threshold
ENABLE High Threshold
ENABLE Leakage Current
V IL(3.3V)
V IH(3.3V)
Logic input is low
Logic input is high at 3.3V
-
2.0
-1
-
1.35
1.6
0
0
0.9
-
-
1
V
V
μA
μA
SVI INTERFACE
PWROK Input Low Threshold
PWROK Input High Threshold
SVC, SVD Input HIGH (VIH)
SVC, SVD Input LOW (VIL)
Schmitt Trigger Input Hysteresis
-
-
1.05
-
-
0.65
0.9
0.87
0.68
0.19
0.8
-
-
0.45
-
V
V
V
V
V
SVD Low Level Output Voltage
SVC, SVD Leakage
3mA Sink Current
EN = 0V, SVC, SVD = 0V
EN = 5V, SVC, SVD = 1.8V
-
-
-
0.1
< -100
< -100
0.285
-
-
V
nA
nA
DIFF AMP
Accuracy
VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V
-2
-
2
mV
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
ISL6265A Gate Driver Timing Diagram
PWM
t PDHU
UGATE
LGATE
t FL
1V
t RU
1V
t FU
t RL
t PDHL
8
FN6884.0
May 11, 2009
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