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参数资料
| 型号： | ISL6271ACR |
| 厂商： | Intersil |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | IC REG PMIC 1BUCK 2LDO 20-QFN |
| 标准包装： | 75 |
| 应用： | 处理器 |
| 电流 - 电源： | 380µA |
| 电源电压： | 2.76 V ~ 5.5 V |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 管件 |
ISL6271A
Internal ESD Structures
The ISL6271A input/output pins are protected from over-
Layout Recommendation
voltage conditions by clamping the pin to one diode drop
above or below the VCC voltage rail. During shutdown it is
possible that the SDA and SCL pins have a voltage greater
than VCC. Under this condition, the ESD diodes will provide
a reverse current path to circuitry on VCC that can act as a
LDO
OUTPUT
CAPS
SINGLE
PT. GND
FB RES
OUTPUT CAP
load on the back-up battery. To avoid this condition, interrupt
VCC from external circuitry if a voltage greater than VCC is
expected on any of the pins identified below.
OUTPUT
INDUCTOR
5x5x1mm
PGND
GND
SOFT-START
CAP
PVCC INPUT CAP
BBAT
VCC
SDA
SCL
EN
VPLL
VSRAM
SOFT
GND
GND
PVCC
LVCC
VOUT
FB
PGOOD
BFLT#
VCC LPF
FIGURE 27. COMPONENT PLACEMENT AND TOP COPPER
Since the ISL6271A can operate at a high switching
frequency, it is especially important to apply good layout
practices. Decoupling of the regulator ’s input voltage
(PVCC) and minimizing the loop area associated with the
phase node output filter is essential for reliable operation.
Return currents from the load should find a low impedance
path to the PGND pin on the IC (Pin 8). Ideally, the core
voltage would be distributed to the embedded processor on
a low impedance power plane; however, a 30-50mil, short
trace should be sufficient. When implementing DVM it is
important to minimize inductance between the load and the
output filter. The processors can command slew rates of up
to 200mA/ns and local decoupling at the processor socket is
essential to satisfying this requirement.
References
[1] ISL6292 data sheet - Battery Charger
[2] EL7536 data sheet - System regulator
[3] C-Code examples for PWR_I2C bus communication -
Intersil support documentation available upon request.
FIGURE 26. INTERNAL ESD STRUCTURES
15
[4] PHILLIPS I 2 C BUS Specification
[5] http://www.semiconductors.philips.com/buses/i2c/
[6] Technical Brief TB389 “ PCB Land Pattern Design and
Surface Mount Guidelines for MLF Packages”
FN9171.1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6271ACR-T | 功能描述:IC PMIC XSCALE PROCESSOR 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| ISL6271ACRZ | 功能描述:直流/直流开关调节器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6271ACRZ-T | 功能描述:直流/直流开关调节器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6271AEVAL1 | 功能描述:EVALUATION BOARD FOR ISL6271A RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6271CR | 制造商:Rochester Electronics LLC 功能描述:PLL & SRAM REGULATOR FOR INTEL PROCESSORS - Bulk 制造商:Intersil Corporation 功能描述: |
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