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参数资料
| 型号： | ISL6271ACR |
| 厂商： | Intersil |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC REG PMIC 1BUCK 2LDO 20-QFN |
| 标准包装： | 75 |
| 应用： | 处理器 |
| 电流 - 电源： | 380µA |
| 电源电压： | 2.76 V ~ 5.5 V |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 管件 |
ISL6271A
Typical Operating Performance
(Continued)
Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made up of a 4.7μH drumcore with 100m ? of
DCR and an output capacitance of 10μF. X5R; Rcomp = 50k ? , Vin = 3.6V unless otherwise noted.
PGOOD
VOUT
EN
PGOOD
VOUT
PHASE
PHASE
Forced PGOOD fault. Converter operating in CCM at 420mA prior to
applying a 320mA transient step. This pushes the regulator beyond
the overcurrent threshold of 700mA. The phase node three-stated
and follows Vout to 0V. 20μs/DIV
FIGURE 14. FORCED PGOOD FAULT
Functional Pin Description
PVCC - Input power to the core switching regulator. This
voltage is typically supplied by a the primary, single-cell
Li-ion battery or power adapter.
VCC. Voltage source for control circuitry. Must be held within
0.3V of PVCC.
BBAT. Secondary back-up voltage used to provide an
indication of the main battery status when the main battery is
low or absent. BBAT is typically a coin cell device and must
be maintained between 1.5V and 3.75V if it is not connected
to VCC pin. Connect it to VCC if BFLT# function is not used.
PHASE. The output switching node that connects to the
output inductor to generate the processor core voltage.
VOUT. Output voltage of the core regulator. Programmable
from 0.85 to 1.6V via the integrated I 2 C bus or VID pins.
LVCC. Input voltage to the VSRAM and VPLL LDO pass
elements. To minimize power loss across the pass element
this should be tied to a pre-regulated system voltage
between 1.8V and 2.5V. LVCC can operate from the main
battery input when lower voltages are unavailable.
VPLL. 1.3V LDO regulator designed to supply power to the
phase-locked loop circuitry internal to the microprocessor.
VSRAM. 1.1V LDO regulator designed to supply power to
the microprocessor SRAM circuitry.
FB. Core voltage feedback (to the error amplifier) via an
external compensation resistor.
SOFT. An external capacitor connected between this pin and
ground controls the regulators output rise time. The start-up
ramp begins when VCC reaches its power-on-reset (POR)
rising threshold and the EN pin is high.
7
PGOOD delay = 186ns from disable.
Vout = 0.85V prior to EN going low, 400ns/DIV
FIGURE 15. PGOOD DELAY
EN - The ISL6271A outputs are enabled when a voltage
greater than 2V is applied to the EN pin. The core regulator
output MOSFETs bridge is turned off and the LDOs are
disabled when EN is pulled low.
BFLT# - Battery fault indicator. A high level indicates the
adequacy of the battery for regulator start-up. Designed to
interface with the processor General Purpose IO, this pin is
actively pulled low when the main battery is absent.
PGOOD - An open-drain output that indicates the status of
the three regulators. It is pulled low when any of the regulators
are outside their voltage tolerances.
VIDEN - Pull this pin low to enable I 2 C communication.
Connecting this pin to VCC disables the I 2 C bus and
enables the VID inputs. In this mode the slew rate is fixed at
a value determined by the soft-start capacitor.
SCL (VID0) - This is a dual function pin. When VIDEN is low
it acts as the I 2 C clock input (SCL). When VIDEN is high this
pin acts as bit 0 to the VID DAC.
SDA (VID1) - This is a dual function pin. When VIDEN is low
it acts as the I 2 C data/address line (SDA) used to transfer
voltage level and slew rate instructions to the ISL6271A.
When VIDEN is high this pin acts as bit 1 to the VID DAC.
VID2, VID3 - VID inputs to the error amplifier reference DAC.
Used to control the core voltage when VIDEN is high.
GND - Device signal ground. Connected to PGND at a
single point to avoid ground loops.
PGND - Power ground return connection for the internal
synchronous rectifier.
FN9171.1
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| ISL6271ACR-T | 功能描述:IC PMIC XSCALE PROCESSOR 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| ISL6271ACRZ | 功能描述:直流/直流开关调节器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6271ACRZ-T | 功能描述:直流/直流开关调节器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6271AEVAL1 | 功能描述:EVALUATION BOARD FOR ISL6271A RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6271CR | 制造商:Rochester Electronics LLC 功能描述:PLL & SRAM REGULATOR FOR INTEL PROCESSORS - Bulk 制造商:Intersil Corporation 功能描述: |
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