参数资料
| 型号： | ISL62771IRTZ |
| 厂商： | Intersil |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 40TQFN |
| 标准包装： | 60 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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ISL62771
As the load current increases from zero, the output voltage
droops from the VID programmed value by an amount
proportional to the load current, to achieve the load line.
Phase Current Balancing
I sum = ----------- (EQ. 1)
The ISL62771 can sense the inductor current through the
intrinsic DC Resistance (DCR) of the inductors, as shown in
Figures 3 and 5, or through resistors in series with the inductors
as shown in Figure 4. In both methods, capacitor C n voltage
represents the total inductor current. An amplifier converts C n
voltage into an internal current source with the gain set by
resistor R i , see Equation 1. This ISUM current is used for load line
V Cn
R i
INTERNAL
TO IC
ISEN2
ISEN1
PHASE2
R isen
C isen
PHASE1
R isen
C isen
L2
L1
I L2
I L1
R dcr2
R dcr1
R pcb2
R pcb1
V O
implementation, current monitoring on the IMON pins and
overcurrent protection.
Figure 13 shows the load-line implementation. The ISL62771
drives a current source (I droop ) out of the FB pin, as described by
Equation 2.
FIGURE 14. CURRENT BALANCING CIRCUIT
The ISL62771 monitors individual phase average current by
monitoring the ISEN1 and ISEN2 voltages. Figure 14 shows the
recommended current balancing circuit for DCR sensing. Each
phase node voltage is averaged by a low-pass filter consisting of
I droop = --- xI sum = --- x -----------
R i
4 4
5 5 V Cn
(EQ. 2)
R isen and C isen , and is presented to the corresponding ISEN pin.
R isen should be routed to the inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR.
When using inductor DCR current sensing, a single NTC element
Equations 6 through 7 give the ISEN pin voltages:
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
(EQ. 6)
(EQ. 7)
I droop flows through resistor R droop and creates a voltage drop as
shown in Equation 3.
V droop = R droop × I droop (EQ. 3)
V droop is the droop voltage required to implement load line.
Changing R droop or scaling I droop can change the load line slope.
Since I sum sets the overcurrent protection level, it is
recommended to first scale I sum based on OCP requirement,
then select an appropriate R droop value to obtain the desired
load line slope.
Differential Sensing
Figure 13 also shows the differential voltage sensing scheme.
where R dcr1 and R dcr2 are inductor DCR; R pcb1 and R pcb2 are
parasitic PCB DCR between the inductor output side pad and the
output voltage rail; and I L1 and I L2 are inductor average currents.
The ISL62771 adjusts the phase pulse-width relative to the other
phases to make V ISEN1 = V ISEN2 , thus to achieve I L1 = I L2 , when
R dcr1 = R dcr2 and R pcb1 = R pcb2 .
Using the same components for L1 and L2 provides a good
match of R dcr1 and R dcr2 . Board layout determines R pcb1 and
R pcb2 . It is recommended to have a symmetrical layout for the
power delivery path between each inductor and the output
voltage rail, such that R pcb1 = R pcb2 .
VCC SENSE and VSS SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS SENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 4:
ISEN2
V2p
PHASE2
R isen
R isen
L2
I L2
R dcr2
V 2n
R pcb2
Vo
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 4)
INTERNAL
TO IC
C isen R isen
PHASE1 V1p
L1
R dcr1
R pcb1
Rewriting Equation 4 and substituting Equation 3 gives
Equation 5. The exact equation required for load-line
implementation.
ISEN1
C isen
R isen
R isen
R isen
I L1
V 1n
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 5)
The VCC SENSE and VSS SENSE signals come from the processor die.
The feedback is an open circuit in the absence of the processor. As
Figure 13 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10 Ω ~100 Ω , provide voltage
feedback if the system is powered up without a processor installed.
17
FIGURE 15. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 14, asymmetric layout causes
different R pcb1 and R pcb2 values, thus creating a current
imbalance. Figure 15 shows a differential sensing current
FN8321.2
September 12, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL62771IRTZ-T | 功能描述:IC PWM CTRLR MULTIPHASE 40TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:Robust Ripple Regulator™ (R³) 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL62773 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiphase PWM Regulator for AMD Fusiona?￠ Desktop CPUs Using SVI 2.0 |
| ISL62773HRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773IRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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