参数资料
型号: ISL62771IRTZ
厂商: Intersil
文件页数: 19/36页
文件大小: 0K
描述: IC PWM CTRLR MULTIPHASE 40TQFN
标准包装: 60
系列: Robust Ripple Regulator™ (R³)
应用: 控制器,AMD Fusion? SVI 2.0 CPU GPU
输入电压: 4.5 V ~ 25 V
输出数: 2
输出电压: 0.006 V ~ 1.55 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
ISL62771
Modes of Operation
TABLE 1. CORE VR MODES OF OPERATION
PSL0_L &
IMON OCP
THRESHOLD
VID transitions, the output voltage decays to the lower VID value
at the slew rate determined by the load.
The R 3 ? modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
CONFIG.
ISEN2
PSI1_L
MODE
(V)
change.
2-phase Core To Power
VR Config. Stage
1-phase Core Tied to 5V
VR Config.
11
01
00
11
01
2-phase CCM
1-phase DE
1-phase DE
1-phase CCM
1-phase DE
1.5
1.5
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative, and the amount is the
01
1-phase DE
00 1-phase DE
The Core VR can be configured for 2- or 1-phase operation.
Table 1 shows Core VR configurations and operational modes,
programmed by the ISEN2 pin status and the PSL0_L & PSL1_L
commands via the SVI 2 interface, see Table 9.
For a 1-phase configuration, tie the ISEN2 pin to 5V. In this
configuration, only Phase 1 is active.
For 2-phase configurations, the Core VR operates in 2-phase CCM
with PSI0_L and PSI_L both high. If PSI0_L is taken low via the
SVI 2 interface, the Core VR sheds Phase 2 and the Core VR
enters 1-phase DE mode. When both PSI0_L and PSI1_L are
taken low, the Core VR continues to operate in the 1-phase DE
mode.
In a 1-phase configuration, the Core VR operates in 1-phase CCM
and enters 1-phase DE when PSI0_L is taken low and continues
to operate in this mode when both PSI0_l and PSI1_L are taken
low.
The Core VR can be disabled completely by connecting ISEN1 to
+5V.
ISL62771 Northbridge VR operates in 1-phase CCM.
Table 2 shows the Northbridge VR operational modes, which are
programmed by the PSI0_L and PSI1_L bits of the SVI 2
command.
TABLE 2. NORTHBRIDGE VR MODES OF OPERATION
PSL0_L and IMON OCP
CONFIG. PSI1_L MODE Threshold
1-phase NB VR 11 1-phase CCM 1.5V
Config.
MOSFET r DS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the zero
crossing point of the inductor current. If the inductor current has
not reached zero when the low-side MOSFET turns off, it will flow
through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it will flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET. To
minimize the body diode-related loss, the controller also adjusts
the phase comparator threshold voltage accordingly in iterative
steps such that the low-side MOSFET body diode conducts for
approximately 40ns.
Resistor Configuration Options
The ISL62771 uses the COMP and COMP_NB pins to configure
some functionality within the IC. Resistors from these pins to GND
are read during the first portion of the soft-start sequence. The
following sections outline how to select the resistor values for each
of these pins to correctly program the output voltage offset of each
output and switching frequency used for both VRs.
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the COMP pin and the Northbridge in a
similar manner from the COMP_NB pin. Table 3 provides the
resistor value to select the desired output voltage offset. The 1%
tolerance resistor value shown in the table must be used to
00
1-phase DE
program the corresponding Core or NB output voltage offset. The
MIN and MAX tolerance values provide margin to insure the 1%
The Northbridge VR operates in 1-phase CCM and enters 1-phase
DE when PSI0_L goes low and remains in this mode of operation
when both PSI0_L and PSI1_L are low.
tolerance resistor will be read correctly.
TABLE 3. COMP and COMP_NB OUTPUT VOLTAGE OFFSET
SELECTION
The Core and Northbridge VRs have an overcurrent threshold of
1.5V on IMON and IMON_NB respectively and this level does not
RESISTOR VALUE [ k Ω ]
COMP
COMP_NB
vary based on channel configuration. See “Overcurrent” on
page 25 for more details.
Dynamic Operation
Core VR and Northbridge VR behave the same during dynamic
operation. The controller responds to VID-on-the-fly changes by
slewing to the new voltage at a fixed slew rate. During negative
MIN
TOLERANCE
5.54
7.76
11.33
16.65
1% TOLERANCE
VALUE
5.62
7.87
11.5
16.9
MAX
TOLERANCE
5.70
7.98
11.67
17.15
V CORE OFFSET
[mV]
-43.75
-37.5
-31.25
-25
OFFSET
[mV]
18.75
31.25
43.76
50
19
FN8321.2
September 12, 2013
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