参数资料
型号: ISL6312AIRZ
厂商: Intersil
文件页数: 20/35页
文件大小: 0K
描述: IC CTRLR PWM 4PHASE BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR10、VR11、AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.38 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6312A
INTEL DYNAMIC VID TRANSITIONS
FB
When in Intel VR10 or VR11 mode the ISL6312A checks the
-
V OFS
+
R FB
I OFS
E/A
VID inputs on the positive edge of an internal 3MHz clock. If a
new code is established and it remains stable for 3
VDIFF
1:1
CURRENT
MIRROR
REF
consecutive readings (1μs to 1.33μs), the ISL6312A
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
VCC
I OFS
-
incrementing or decrementing one VID step at a time. In VR10
and VR11 settings, the ISL6312A will immediately change the
internal DAC reference to the new requested value as soon as
the request is validated, which means the fastest
recommended rate at which a bit change can occur is once
every 2μs. In cases where the reference step is too large, the
R OFS
OFS
ISL6312A
1.6V
+
sudden change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VCC
smoothing network is required. This network is composed of
an internal 1k Ω resistor between the DAC and the REF pin,
and the external capacitor C REF , between the REF pin and
ground. The selection of C REF is based on the time duration
for 1 bit VID change and the allowable delay time.
+
V OFS
-
FB
R FB
I OFS
E/A
Assuming the microprocessor controls the VID change at 1
bit every T VID , the relationship between C REF and T VID is
given by Equation 14.
VDIFF
VCC
REF
C REF = 0.001 ( S ) ? T VID
(EQ. 14)
As an example, for a VID step change rate of 5 μ s per bit, the
1:1
CURRENT
MIRROR
I OFS
value of C REF is 5600pF based on Equation 14.
AMD DYNAMIC VID TRANSITIONS
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6312A responds differently to a dynamic VID change then
when in Intel VR10 or VR11 mode. In the AMD modes the
R OFS
OFS
GND
ISL6312A
+
0.4V
-
GND
ISL6312A still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
changed by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(1 μ s to 1.33 μ s), the ISL6312A recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
t DVID = -------------------------- ? ? --------------------- ?
1 Δ V VID
3 ? 0.00625 ?
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6312A
to do this by making changes to the VID inputs. The ISL6312A
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6312A is operating in
determines how the controller responds to a dynamic VID
change.
20
frequency of 330kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, t DVID , is dependent
only on the size of the VID change ( Δ V VID ).
The time required for a ISL6312A-based converter in AMD 5-bit
DAC configuration to make a 1.1V to 1.5V reference voltage
change is about 194μs, as calculated using Equation 15.
(EQ. 15)
330 × 10
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
1k Ω resistor between the DAC and the REF pin, and the
external capacitor C REF , between the REF pin and ground.
For AMD VID transitions C REF should be a 1000pF capacitor.
FN9290.5
February 1, 2011
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