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参数资料
| 型号： | ISL6316CRZ |
| 厂商： | Intersil |
| 文件页数： | 10/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6316
Electrical Specifications
Operating Conditions: V CC = 5V, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER GOOD AND PROTECTION MONITORS
Leakage Current of PGOOD
PGOOD Low Voltage
Undervoltage Threshold
PFGOOD Reset Voltage
Overvoltage Protection Threshold
With externally pull-up resistor connected to VCC
I PGOOD = 4mA
VDIFF Falling
VDIFF Rising
Before valid VID
-
-
48
58
1.250
-
-
50
60
1.275
30
0.3
52
62
1.300
μ A
V
%VID
%VID
V
Overvoltage Protection Reset Threshold
After valid VID, the voltage above VID
150
0.38
175
0.40
200
0.42
mV
V
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Spec guaranteed by design.
5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
Functional Pin Description
VCC
Supplies the power necessary to operate the chip. The
controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply.
GND
Bias and reference ground for the IC. The bottom metal base
of ISL6316 is the GND.
EN_PWR
This pin is a threshold-sensitive enable input for the controller.
Connecting the 12V supply to EN_PWR through an
appropriate resistor divider provides a means to synchronize
power-up of the controller and the MOSFET driver ICs. When
EN_PWR is driven above 0.875V, the ISL6316 is active
depending on status of EN_VTT, the internal POR, and
pending fault states. Driving EN_PWR below 0.745V will clear
all fault states and prime the ISL6316 to soft-start when re-
enabled.
EN_VTT
This pin is another threshold-sensitive enable input for the
controller. It’s typically connected to VTT output of VTT
voltage regulator in the computer mother board. When
EN_VTT is driven above 0.875V, the ISL6316 is active
depending on status of ENLL, the internal POR, and pending
fault states. Driving EN_VTT below 0.745V will clear all fault
states and prime the ISL6316 to soft-start when re-enabled.
FS
Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching
frequency. The relationship between the value of the resistor
10
and the switching frequency will be described by approximate
equations.
SS
Use this pin to set up the desired start-up oscillator frequency.
A resistor, placed from SS to ground will set up the soft-start
ramp rate.The relationship between the value of the resistor
and the soft-start ramp up time will be described by
approximate equation.
VID5, VID4, VID3, VID2, VID1 and VID0
These are the inputs to the internal DAC that generates the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active-pull-up outputs. All VID pins have 40μA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up externally as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND
VSEN and RGND form the precision differential remote-sense
amplifier. This amplifier converts the differential voltage of the
remote output to a single-ended voltage referenced to local
ground. VDIFF is the amplifier’s output and the input to the
regulation and protection circuitry. Connect VSEN and RGND
to the sense pins of the remote load.
FB and COMP
Inverting input and output of the error amplifier respectively.
FB can be connected to VDIFF through a resistor. A properly
chosen resistor between VDIFF and FB can set the load line
(droop), when IDROOP pin is tied to FB pin. The droop scale
factor is set by the ratio of the ISEN resistors and the inductor
DCR or the lower MOSFET r DS(ON) . COMP is tied back to FB
through an external R-C network to compensate the regulator.
FN9227.1
December 12, 2006
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