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参数资料
| 型号： | ISL6316CRZ |
| 厂商： | Intersil |
| 文件页数： | 25/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6316
C 2 (OPTIONAL)
C 2
R C
C C
COMP
R C
C C
COMP
FB
C 1
FB
R FB
+
V DROOP
IDROOP
R 1
R FB
IDROOP
-
VDIFF
VDIFF
FIGURE 20. COMPENSATION CIRCUIT FOR ISL6316 BASED
CONVERTER WITHOUT LOAD-LINE
FIGURE 19. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6316 CIRCUIT
The feedback resistor, R FB , has already been chosen as
outlined in Load-Line Regulation Resistor . Select a target
bandwidth for the compensated system, f 0 . The target
bandwidth must be large enough to assure adequate transient
performance, but smaller than 1/3 of the per-channel
switching frequency. The values of the compensation
components depend on the relationships of f 0 to the L-C pole
frequency and the ESR zero frequency. For each of the three
cases which follow, there is a separate set of equations for the
compensation components.
REGULATION
In Equation 32, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications .
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C 2 , and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
------------------- > f 0
R C = R FB ---------------------------------------
0.75V
2 π V P-P R FB f 0
------------------- ≤ f 0 < ------------------------------
Case 1:
Case 2:
1
2 π LC
2 π f 0 V P-P LC
IN
0.75V IN
C C = --------------------------------------
1 1
2 π LC 2 π C ( ESR )
Once selected, the compensation values in Equation 32
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 32 unless some performance issue is noted.
0.75 V IN
C C = ---------------------------------------------------------------
P-P R FB LC
( 2 π ) 2 f 2 V
V P-P ( 2 π ) 2 f 02 LC
R C = R FB ----------------------------------------------
0.75V IN
0
(EQ. 32)
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 20, provides the
necessary compensation.
f 0 > ------------------------------
0.75 V IN ( ESR )
2 π V P-P R FB f 0 L
Case 3:
1
2 π C ( ESR )
2 π f 0 V P-P L
R C = R FB ------------------------------------------
0.75V IN ( ESR ) C
C C = -------------------------------------------------
25
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at the
error-amplifier high-order pole and zero frequencies. A good
general rule is to choose f HF = 10f 0 , but it can be higher if
desired. Choosing f HF to be lower than 10f 0 can cause
problems with too much phase shift below the system
bandwidth.
FN9227.1
December 12, 2006
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