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| 型号： | ISL6316CRZ |
| 厂商： | Intersil |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6316
voltage under load can effectively be level shifted down so
that a larger positive spike can be sustained without crossing
the upper specification limit.
FB
As shown in Figure 8, a current proportional to the average
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
DYNAMIC
VID D/A
DAC
R REF
creating an output voltage droop with a steady-state value
defined as:
E/A
REF
V DROOP = I AVG R FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate sample
current expression defined by the current sense method
VCC
OR
GND
V OUT = V REF – V OFS – ? ------------- ------------------ R FB ?
employed.
? I OUT R X ?
? N R ISEN ?
(EQ. 9)
1.6V
-
+
0.4V
+
-
ISL6316
OFS
R OFS
Where V REF is the reference voltage, V OFS is the
VCC
GND
programmed offset voltage, I OUT is the total output current of
the converter, R ISEN is the sense resistor connected to the
ISEN+ pin, and R FB is the feedback resistor, N is the active
channel number, and R X is the DCR, r DS(ON) , or R SENSE
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
R LL = ------------ ------------------
R ISEN
N
R FB R X
(EQ. 10)
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
Output-Voltage Offset Programming
The ISL6316 allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into OFS. If R OFS
is connected to ground, the voltage across it is regulated to
0.4V, and I OFS flows out of OFS. A resistor between DAC and
REF, R REF , is selected so that the product (I OFS x R OFS ) is
equal to the desired offset voltage. These functions are shown
in Figure 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
function of the core-voltage regulator.
The ISL6316 checks the VID inputs six times every switching
cycle. If the VID code is found to have been changed, the
controller waits for half of a switching cycle before executing a
6.25mV step change. If the difference between DAC level and
the new VID code changes during the half-cycle waiting
period, no change to the DAC output is made. If the VID code
is more than 1-bit higher or lower than the DAC (not
recommended), the controller will execute 6.26mV step
change six times per cycle until VID and DAC are equal.
Therefore it is important to carefully control the rate of VID
stepping in 1-bit increments.
R OFS = ------------------------------
R OFS = ------------------------------
For Positive Offset (connect R OFS to VCC):
1.6 × R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 × R REF
V OFFSET
17
(EQ. 11)
(EQ. 12)
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R REF and C REF , can be used. The selection of
R REF is based on the desired offset voltage as detailed above
in Output-Voltage Offset Programming . The selection of C REF
is based on the time duration for 1-bit VID change and the
allowable delay time.
FN9227.1
December 12, 2006
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| ISL6322CRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6322CRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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