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| 型号： | ISL6316CRZ |
| 厂商： | Intersil |
| 文件页数： | 26/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6316
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 33, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 33.
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
R 1 = R FB -----------------------------------------
Δ V ≈ ( ESL ) ----- + ( ESR ) Δ I
C ( ESR )
LC – C ( ESR )
di
dt
(EQ. 34)
C 1 = -----------------------------------------
( 2 π ) 2 f 0 f HF LCR FB V P-P
V P-P ? 2 π ? f 0 f HF LCR FB
R C = ---------------------------------------------------------------------
0.75 V IN ? 2 π f HF LC – 1 ?
LC – C ( ESR )
R FB
0.75V IN
C 2 = ---------------------------------------------------------------------
2
? ?
? ?
The filter capacitor must have sufficiently low ESL and ESR so
that Δ V < Δ V MAX .
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited high-
frequency performance. Minimizing the ESL of the high-
frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
0.75V IN ? 2 π f
( 2 π ) 2 f 0 f HF LCR FB V P-P
?
? HF LC – 1 ?
C C = ---------------------------------------------------------------------
(EQ. 33)
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
– N V OUT ? V OUT
? V
L ≥ ( ESR ) ------------------------------------------------------------
? IN ?
In Equation 33, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications .
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must supply
or sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, Δ I;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, Δ V MAX .
ESR equal to I C,P-P (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V P-P(MAX) , determines the lower limit on the inductance.
(EQ. 35)
f S V IN V P-P ( MAX )
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient,
the capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than Δ V MAX . This
places an upper limit on inductance.
Equation 36 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 37
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of the
two results. In each equation, L is the per-channel inductance,
C is the total output capacitance, and N is the number of
active channels.
L ≤ --------------------- Δ V MAX – Δ I ( ESR )
L ≤ -------------------------- Δ V MAX – Δ I ( ESR ) ? V IN – V O ?
( Δ I ) 2
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
26
2NCV O
( Δ I ) 2
( 1.25 ) NC
? ?
(EQ. 36)
(EQ. 37)
FN9227.1
December 12, 2006
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