参数资料
| 型号： | ISL6322GIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6322G
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES (Continued)
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
VID5
1
1
1
VID4
0
0
0
VID3
1
1
1
VID2
0
1
1
VID1
1
0
0
VID0
1
0
1
VDAC
0.6250
0.6125
0.6000
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through
an external resistor.
EXTERNAL CIRCUIT
ISL6322 INTERNAL CIRCUIT
1
0
1
1
1
0
0.5875
1
1
0
1
1
0
1
0
1
0
1
0
0.5750
0.5625
COMP
VID DAC
1
1
1
1
0
0
0
0
0
1
1
0
0.5500
0.5375
C C
REF
1k
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
0.5250
0.5125
0.5000
R C
C REF
FB
ERROR
AMPLIFIER
+
-
V COMP
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
0.4875
0.4750
0.4625
R FB
+
V OFS
-
VDIFF
I OFS
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0.4500
0.4375
0.4250
V OUT +
V OUT -
VSEN
RGND
+
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0.4125
0.4000
0.3875
0.3750
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Voltage Regulation
The integrating compensation network shown in Figure 6
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6322G to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is compared to the
triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
Output-Voltage Offset Programming
The ISL6322G allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the FB pin.
If R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (I OFS x R FB ). These functions are
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use Equations 9 and 10 to set R OFS :
V OUT = V REF – V OFS
R OFS = --------------------------
R OFS = --------------------------
circuitry that controls voltage regulation is illustrated in
Figure 6.
(EQ. 8)
The ISL6322G incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point
19
For Negative Offset (connect R OFS to GND):
0.4 ? R FB
V OFFSET
For Positive Offset (connect R OFS to VCC):
1.6 ? R FB
V OFFSET
(EQ. 9)
(EQ. 10)
FN6715.0
May 22, 2008
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