参数资料
| 型号： | ISL6322GIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 22/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6322G
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC and the VID pins. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6322G is released
from shutdown mode to begin the soft-start startup
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6322G is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6322G will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6322G in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
For Intel VR10, VR11 and AMD 6-bit modes of operation
these are the only conditions that must be met for the
controller to immediately begin the soft-start sequence. If
running in AMD 5-bit mode of operation there is one more
condition that must be met:
4. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
VOUT, 500mV/DIV
t D1
t D2
t D3
t D4
t D5
ISL6322G INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC
+ 12 V
EN_VTT
PGOOD
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.85V
EN
10.7k Ω
1.40k Ω
500μs/DIV
FIGURE 11. INTEL SOFT-START WAVEFORMS
For the Intel VR10 and VR11 modes of operation, the
soft-start sequence is composed of four periods, as shown in
Figure 11. Once the ISL6322G is released from shutdown
period t D1 . After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
SOFT-START
AND
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
3. The driver bias voltage applied at the PVCC pin must
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period t D3 . At the end of t D3 period,
ISL6322G will read the VID signals. If the VID code is valid,
ISL6322G will initiate the second soft-start ramp until the
output voltage reaches the VID voltage plus/minus any offset
voltage.
The soft-start time is the sum of the four periods as shown in
Equation 14.
assure that once enabled, the ISL6322G will not
22
T SS = t D1 + t D2 + t D3 + t D4
(EQ. 14)
FN6715.0
May 22, 2008
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