参数资料
| 型号： | ISL6322GIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 27/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6322G
.
Writing to the Internal Registers
SCL
1
2
8
9
In order to change any of the four operating parameters via
the I 2 C bus, the internal registers must be written to. The two
registers inside the ISL6322G can be written individually with
SDA
MSB
two separate write transactions or sequentially with one write
transaction by sending two data bytes as described below.
START
ACKNOWLEDGE
To write to a single register in the ISL6322G, the master
FROM SLAVE
FIGURE 18. ACKNOWLEDGE ON THE I 2 C BUS
ISL6322G I 2 C Slave Address
All devices on the I 2 C bus must have a 7-bit I 2 C address in
order to be recognized. The ISL6322G has two user
selectable addresses to ensure it does not interfere with
other devices on the bus. The address is programmed via
the R ss resistor on the SS/RST/A0 pin. Placing the R ss
resistor from the SS/RST/A0 pin to ground sets the I 2 C
address to be 1000_110. If the R ss resistor is placed from
the SS/RST/A0 pin to VCC the address is 1000_111.
Please note that the I 2 C address of the ISL6322G is
programmed from the SS/RST/A0 pin as soon as VCC rises
above the POR threshold. The ISL6322G’s I 2 C address
stays the same and can not be reprogrammed until VCC
falls back below the POR falling threshold.
Communicating Over the I 2 C Bus
Two transactions are supported on the I 2 C interface:
1. Write register,
2. Read register from current address.
All transactions start with a control byte sent from the I 2 C
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write or 1 for a read. If any
slaves on the I 2 C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last clock
cycle in the control byte. If no slaves exist at that address or are
not ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition.
Once the control byte is sent, and the ISL6322G
acknowledges it, the 2nd byte sent by the master must be a
register address byte. This register address byte tells the
ISL6322G which one of the two internal registers it wants to
write to or read from. The address of the first internal
register, RGS1, is 0000_0000. This register sets the Voltage
Margining Offset. The address of the second internal
register, RGS2, is 0000_0001. This register sets the
Adaptive Deadtime Control, Overvoltage Protection, and
Switching Frequency parameters. Once the ISL6322G
receives a correct register address byte, it responds with an
acknowledge.
27
sends a control byte with the R/W bit set to 0, indicating a
write. If it receives an Acknowledge from the ISL6322G, it
sends a register address byte representing the internal
register it wants to write to (0000_0000 for RGS1 or
0000_0001 for RGS2). The ISL6322G will respond with an
Acknowledge. The master then sends a byte representing
the data byte to be written into the desired register. The
ISL6322G will respond with an Acknowledge. The master
then issues a Stop condition, indicating to the ISL6322G that
the current transaction is complete. Once this transaction
completes, the ISL6322G will immediately update and
change the operating parameters on-the-fly.
It is also possible to write to both registers sequentially. To
do this the master must write to register RGS1 first. This
transaction begins with the master sending a control byte
with the R/W bit set to 0. If it receives an Acknowledge from
the ISL6322G, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6322G will
respond with an Acknowledge. After sending the data byte to
RGS1 and receiving an Acknowledge from the ISL6322G,
instead of sending a Stop condition, the master sends the
data byte to be stored in register RGS2. The ISL6322G will
respond with an Acknowledge. The master then issues a
Stop condition, indicating to the ISL6322G that the current
transaction is complete. Once this transaction completes the
ISL6322G will immediately update and change the operating
parameters on-the-fly.
FN6715.0
May 22, 2008
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