参数资料
| 型号： | ISL6322GIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 28/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6322G
I 2 C Read and Write Protocol
Write to a Single Register
S
slave_addr + W
A
reg_addr
A
reg_data
A
P
Write to Both Registers
S
slave_addr + W
A
0000_0000
A
reg_RGS1_data
A
reg_RGS2_data
A
P
Read from a Single Register
S
slave_addr + W
A
reg_addr
A
P
S
slave_addr + R
A
reg_data
N
P
Read from Both Registers
S
slave_addr + W
A
0000_0000
A
P
S
slave_addr + R
A
reg_RGS1_data
A
reg_RGS2_data
N
P
Driven by Master
Driven by ISL6322
S = START Condition
P = STOP Condition
A = Acknowledge
N = No Acknowledge
Reading from the Internal Registers
The ISL6322G has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register ’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once
it receives an Acknowledge from the ISL6322G, it sends a
register address byte representing the internal register it
wants to read from (0000_0000 for RGS1 or 0000_0001 for
RGS2). The ISL6322G will respond with an Acknowledge.
The master must then respond with a Stop condition. After
the Stop condition, the master follows with a new Start
condition, and then sends a new control byte with the R/W
bit set to 1, indicating a read. The ISL6322G will then
respond by sending the master an Acknowledge, followed by
the data byte stored in that register. The master must then
send a Not Acknowledge followed by a Stop command,
which will complete the read transaction.
Resetting the Internal Registers
The ISL6322G’s two internal I 2 C registers always initialize to
0000_0000 when the controller first receives power. Once
the voltage on the VCC pin rises above the POR rising
threshold level, these registers can be changed at any time
via the I 2 C interface. If the voltage on the VCC pin falls
below the POR falling threshold, the internal registers are
automatically reset to 0000_0000.
It is possible to reset the internal registers without powering
down the controller and without requiring the controller to
stop regulating and soft-start again. This can be done by one
of two methods. The first method is to simply write to the
internal registers over the I 2 C interface to be 0000_0000.
The other method is pull the voltage on the SS/RST/A0 pin
down below 0.4V. This will immediately reset the internal
registers to 0000_0000 and will not stop the controller from
regulating the output voltage or cause soft-start to recycle.
TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING
OFFSET)
It is also possible for both registers to be read consecutively.
To do this the master must read from register RGS1 first.
This transaction begins with the master sending a control
byte with the R/W bit set to 0. If it receives an Acknowledge
from the ISL6322G, it sends the register address byte
0000_0000, representing the internal register RGS1. The
ISL6322G will respond with an Acknowledge. The master
must then respond with a Stop condition. After the Stop
condition the master follows with a new Start condition, and
then sends a new control byte with the R/W bit set to 1,
indicating a read. The ISL6322G will then respond by
sending the master an Acknowledge, followed by the data
byte stored in register RGS. The master must then send an
Acknowledge, and after doing so, the ISL6322G will respond
by sending the data byte stored in register RGS2. The
master must then send a Not Acknowledge followed by a
BIT7
X
x
x
x
x
x
x
x
x
x
x
BIT6
X
x
x
x
x
x
x
x
x
x
x
BIT5
VO5
0
0
0
0
0
0
0
0
0
0
BIT4
VO4
0
0
0
0
0
0
0
0
0
0
BIT3
VO3
0
0
0
0
0
0
0
0
1
1
BIT2
VO2
0
0
0
0
1
1
1
1
0
0
BIT1
VO1
0
0
1
1
0
0
1
1
0
0
BIT0
VO0
0
1
0
1
0
1
0
1
0
1
V OFFSET
(mV)
0.0
12.5
25.0
37.5
50.00
62.5
75.0
87.5
100.0
112.5
Stop command, which will complete the read transaction.
28
FN6715.0
May 22, 2008
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