参数资料
| 型号： | ISL6329IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
ISL6329
Pre-Biased Soft-Start
The ISL6329 also has the ability to start-up into a pre-charged
output, without causing any unnecessary disturbance. The FB pin
is monitored during soft-start, and should it be higher than the
equivalent internal ramping reference voltage, the output drives
hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by the
DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at the
end of the soft-start period, leading to an abrupt correction in the
output voltage down to the DAC-set level.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
Overvoltage Protection
The ISL6329 constantly monitors the sensed output voltage on the
VSEN pin to detect if an overvoltage event occurs. When the output
voltage rises above the OVP trip level and exceeds the PGOOD OV
limit actions are taken by the ISL6329 to protect the
microprocessor load.
At the inception of an overvoltage event, both on-board lower
gate pins are commanded low as are the active PWM outputs to
the external drivers, the PGOOD signal is driven low, and the
ISL6329 latches off normal PWM action. This turns on the all of
the lower MOSFETs and pulls the output voltage below a level
that might cause damage to the load. The lower MOSFETs
remain driven ON until VDIFF falls below 400mV. The ISL6329
will continue to protect the load in this fashion as long as the
overvoltage condition recurs. Once an overvoltage condition ends
the ISL6329 latches off, and must be reset by toggling POR,
before a soft-start can be re-initiated.
OUTPUT PRECHARGED
BELOW DAC LEVEL
V CORE
400mV/DIV
-
OCL
+
170μA
I 1
100μA
-
OCP
REPEAT FOR EACH
CORE CHANNEL
EN
5V/DIV
100μs/DIV
I NB
NB ONLY
+
-
OCP
+
100μA
I AVG
CORE ONLY
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6329-BASED
MULTIPHASE CONVERTER
SOFT-START, FAULT
AND CONTROL LOGIC
Both CORE and NB output support start up into a pre-charged
output.
NB ONLY
1.8V
+
OVP
Fault Monitoring and Protection
-
The ISL6329 actively monitors both CORE and NB output voltages
and currents to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to either load. One
ISEN_NB+
DAC - 300mV
-
+
UV
common power good indicator is provided for linking to external
system monitors. The schematic in Figure 13 outlines the
interaction between the fault monitors and the power good signal.
CORE ONLY
1.8V
+
-
OVP
VDDPWRGD
Power Good Signal
DAC + 250mV
-
The power good pin (VDDPWRGD) is an open-drain logic output
that signals whether or not the ISL6329 is regulating both NB
+
OV
and CORE output voltages within the proper levels, and whether
any fault conditions exist. This pin should be tied to a +5V source
through a resistor.
VSEN
DAC - 300mV
-
+
UV
During shutdown and soft-start, VDDPWRGD pulls low and releases
high after a successful soft-start and both output voltages are
operating between the undervoltage and overvoltage limits. PGOOD
transitions low when an undervoltage, overvoltage, or overcurrent
condition is detected on either output or when the controller is
disabled by a POR reset or EN. In the event of an overvoltage or
overcurrent condition, the controller latches off and PGOOD will not
return high. Pending a POR reset of the ISL6329 and successful
soft-start, the PGOOD will return high.
21
ISL6329 INTERNAL CIRCUITRY
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
Pre-POR Overvoltage Protection
Prior to PVCC, VCC and GVOT exceeding their POR levels, the
ISL6329 is designed to protect either load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10k Ω resistor tied from PHASE to LGATE, which turns on
FN7800.0
April 19, 2011
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6333IRZ | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| ISL6334AIRZR5368 | IC CTRLR PWM 4PHASE BUCK 40QFN |
| ISL6334BIRZ-T | IC CTRLR PWM SYNC BUCK 40-QFN |
| ISL6334CRZ | IC CTRLR PWM 4PHASE BUCK 40-QFN |
| ISL6334DIRZ | IC CTRLR PWM 4PHASE VR11.1 40QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6333ACRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333ACRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333AEVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6333AIRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
| ISL6333AIRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。