参数资料
| 型号： | ISL6329IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 28/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
Control. Bits 0 and 1 are for overriding analog programming of
NB droop control. Bits 2 and 3 are for adjusting the droop gain.
Bits 4 and 5 override the analog programming for number of
active phases in Power Savings Mode. This register can only be
written to when PWROK is LOW.
TABLE 11. BITS [7:0] REGISTER RGS5
Bits [7:6] Reserved
techniques referenced below. In addition to this guide, Intersil
provides complete reference designs that include schematics, bills
of materials, and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily on
Bits [5:4]
0x
10
11
Bits [3:2]
00
01
10
11
Bits [1:0]
0x
10
11
Number of Active Phases in Power Savings Mode
No Action (Default)
Num Phases in PSI = 1
Num Phases in PSI = 2
Core Droop Gain Adjust
Droop Current Gain = 1 (Default)
Droop Disabled
Droop Current Gain = 1/2
Droop Current Gain = 1/4
Northbridge Droop Control Override
No Action (Default)
Northbridge Droop Disabled
Northbridge Droop Enabled
the cost analysis which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board, whether through-hole components
are permitted, the total board space available for power-supply
circuitry, and the maximum amount of load current. Generally
speaking, the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount designs
will tend toward the lower end of this current range. If through-
hole MOSFETs and inductors can be used, higher per-phase
currents are possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase, but
these designs require heat sinks and forced air to cool the
MOSFETs, inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
The bits for Register RGS6 control some of the functionality of
the ISL6329 for VID on the Fly Slew Rate and APA. Bits 0 through
3 are reserved. Bit 4 selects whether APA is controlled by
monitoring the VSEN pin or the COMP pin. Bit 5 will
disable/enable APAL and APAH events. Bits 6 and 7 control the
VID on the Fly slew rate. This register can only be written to when
PWROK is Low.
TABLE 12. BITS [7:0] REGISTER RGS6
heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to current
conducted through the channel resistance (r DS(ON) ). In
Equation 23, I M is the maximum continuous output current, I PP
is the peak-to-peak inductor current (see Equation 2), and d is the
duty cycle (V OUT /V IN ).
? I M ? 2 I L , PP ? ( 1 – d )
P LOW , 1 = r DS ( ON ) ? ? ------ ? ? ( 1 – d ) + -------------------------------------
Bits [7:6]
00
VID on the Fly Slew Rate
2.8mV/ μ sec
? N ? 12
(EQ. 23)
01
10
11
Bit 5
0
5.6mV/ μ sec
7.5mV/ μ sec
9.4mV/ μ sec
Enable APAL and APAH Events
Disabled
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-MOSFET
body diode. This term is dependent on the diode forward voltage
at I M , V D(ON) , the switching frequency, f S , and the length of dead
times, t d1 and t d2 , at the beginning and the end of the lower-
MOSFET conduction interval respectively.
? ? ------ + I ---------- ? ? t
? I
+ ? ------ – ---------- ? ? t d2
? N 2 ?
1
Bit 4
ENABLED (Default)
VSEN or COMP APA Monitoring
P
LOW , 2
= V
D ( ON )
? f
S
? IM PP ?
? N 2 ?
d1
?
M I PP
? ?
(EQ. 24)
0
Monitor VSEN (Default)
1
Bits [3:0]
Monitor COMP
Reserved
The total maximum power dissipated in each lower MOSFET is
approximated by the summation of P LOW,1 and P LOW,2 .
UPPER MOSFET POWER CALCULATION
General Design Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills and
28
In addition to r DS(ON) losses, a large portion of the upper-MOSFET
losses are due to currents conducted across the input voltage
(V IN ) during switching. Since a substantially higher portion of the
upper-MOSFET losses are dependent on switching frequency, the
power calculation is more complex. Upper MOSFET losses can be
FN7800.0
April 19, 2011
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| ISL6333ACRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333ACRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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