参数资料
| 型号： | ISL6329IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 24/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
The STOP (P) condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
TABLE 4. I 2 C ADDRESS PROGRAMMING (Continued)
RESISTOR TIED TO RESISTOR VALUE ADDRESS
VCC
50k Ω
1011_110
SDA
VCC
100k Ω
1011_111
Communicating Over the I 2 C Bus
SCL
Two transactions are supported on the I 2 C interface:
S
START
CONDITION
P
STOP
CONDITION
1. Write register
2. Read register from current address.
FIGURE 16. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit.
Data is transferred with the most significant bit first (MSB) and
the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses. The
ninth pulse is the acknowledge bit (A). After the start condition,
the master sends 7 slave address bits and a R/W bit during the
next 8-clock pulses. During the ninth clock pulse, the device that
recognizes its own address holds the data line low to
acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data as described in Figure 17.
All transactions start with a control byte sent from the I 2 C master
device. The control byte begins with a Start condition, followed by
7-bits of slave address. The last bit sent by the master is the R/W
bit and is 0 for a write or 1 for a read. If any slaves on the I 2 C bus
recognize their address, they will Acknowledge by pulling the
serial data line low for the last clock cycle in the control byte. If
no slaves exist at that address or are not ready to communicate,
the data line will be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL6329 acknowledges it,
the 2nd byte sent by the master must be a register address byte.
This register address byte tells the ISL6329 which one of the
internal registers it wants to write to or read from. The address of
the first internal register, RGS0, is 0000_0000. This register sets
the Northbridge Offset, Overvoltage trip point and Power-good trip
level. The address of the second internal register, RGS1, is
0000_0001. This register sets the Core Offset, Overvoltage trip
point and Power-good trip level. The address of the third register,
RGS2, is 0000_0010. The third register is for programming of the
SCL
1
2
8
9
Power Savings Mode features. The fourth register, RGS3
(0000_0011) is Reserved. The fifth register, RGS4 (0000_0100), is
for Phase Control and the GVOT voltage. The sixth register, RGS5
SDA
MSB
(0000_0101), is used to set minimum phases for PSI and APD and
has droop programmability. The seventh register, RGS6
(0000_0110), controls the VID on the Fly slew rate, and various
START
ACKNOWLEDGE
FROM SLAVE
APA programming. It is important to note that RGS4, RGS5 and
RGS6 can only be written to when the PWROK signal to the
FIGURE 17. ACKNOWLEDGE ON THE I 2 C BUS
ISL6329 I 2 C Slave Address
ISL6329 is low. Otherwise, once the ISL6329 receives a correct
register address byte, it responds with an acknowledge.
TABLE 5. I 2 C REGISTER FUNCTIONS
All devices on the I 2 C bus must have a 7-Bit I 2 C address in order
to be recognized. There are 8 selectable address available with
the ISL6329. To program an address, a resistor must be tied
from the I2C_ADDR pin (Pin 52) to either ground or VCC. The
resistor value will determine the address.
TABLE 4. I 2 C ADDRESS PROGRAMMING
REGISTER
RGS0
RGS1
RGS2
RGS3
ADDRESS
0000_0000
0000_0001
0000_0010
0000_0011
FUNCTIONS
Northbridge DAC Offset, OVP, PGOOD
Core DAC Offset, OVP, PGOOD
PSI Mode Functions
Reserved
RESISTOR TIED TO
Ground
Ground
RESISTOR VALUE
0 Ω
20k Ω
ADDRESS
1000_110
1010_110
RGS4
RGS5
RGS6
0000_0100
0000_0101
0000_0110
Phase Control and GVOT
Min Num Phases and Droop Functions
VOF Slew Rate and APA Functions
Ground
Ground
VCC
VCC
24
50k Ω
100k Ω
0 Ω
20k Ω
1001_110
1011_110
1010_110
1010_111
Writing to the Internal Registers
In order to change any of the operating parameters via the I 2 C
bus, the internal registers must be written to. The five registers
inside the ISL6329 can be written individually with separate
write transactions or sequentially with one write transaction.
FN7800.0
April 19, 2011
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