参数资料
| 型号： | ISL6329IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 30/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
V IN
L
C OUT
In Equations 30 and 31, P Qg_Q1 is the total upper gate drive power
loss and P Qg_Q2 is the total lower gate drive power loss; the gate
charge (Q G1 and Q G2 ) is defined at the particular gate to source
drive voltage PVCC in the corresponding MOSFET data sheet; I Q is
the driver total quiescent current with no load at both drive outputs;
N Q1 and N Q2 are the number of upper and lower MOSFETs per
phase, respectively; N PHASE is the number of active phases. The
I Q* VCC product is the quiescent power of the controller without
capacitive load and is typically 75mW at 300kHz.
Inductor DCR Current Sensing Component
Fine Tuning
I
n
UGATE(n)
L
MOSFET DCR V OUT
DRIVER LGATE(n) INDUCTOR
V L (s)
PVCC
BOOT
D
V C (s)
C GD
R 1
C
I n
R HI1
R LO1
PHASE
UGATE
G
R G1
R GI1
C GS
S
C DS
Q1
ISL6329 INTERNAL
CIRCUIT
+
-
ISENn-
ISENn+
C ISEN
R 2
V C (s)
R ISEN
I SEN
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 21. DCR SENSING CONFIGURATION
PVCC
Due to errors in the inductance and/or DCR, it may be necessary
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
S
D
C DS
Q2
to adjust the value of R 1 and R 2 to match the time constants
correctly. The effects of time constant mismatch can be seen in
the form of droop overshoot or undershoot during the initial load
transient spike, as shown in Figure 22. Follow the steps below to
ensure the R-C and inductor L/DCR time constants are matched
accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and Ground for
the duration of this procedure.
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in the
controller itself is the power dissipated in the upper drive path
2. Capture a transient event with the oscilloscope set to about
L/DCR/2 (sec/div). For example, with L = 1 μ H and DCR = 1m Ω ,
set the oscilloscope to 500 μ s/div.
3. Record Δ V1 and Δ V2 as shown in Figure 22.
resistance (P DR_UP ), the lower drive path resistance (P DR_UP ),
and in the boot strap diode (P BOOT ). The rest of the power will be
dissipated by the external gate resistors (R G1 and R G2 ) and the
internal gate resistors (R GI1 and R GI2 ) of the MOSFETs. Figures
19 and 20 show the typical upper and lower gate drives turn-on
transition path. The total power dissipation in the controller itself,
P DR , can be roughly estimated as:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
Δ V 1
Δ V 2
V OUT
P BOOT = ---------------------
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P Qg_Q1
3
? R HI1 R LO1 ? P Qg_Q1
3
(EQ. 32)
Δ I
I TRAN
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R LO2 + R EXT2 ?
R HI2 + R EXT2
? R HI2 R LO2 ? P Qg_Q2
2
FIGURE 22. TIME CONSTANT MISMATCH BEHAVIOR
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
R GI1
Q1
R GI2
Q2
30
FN7800.0
April 19, 2011
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