参数资料
| 型号： | ISL6333IRZ |
| 厂商： | Intersil |
| 文件页数： | 24/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
ISL6333, ISL6333A, ISL6333B, ISL6333C
TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)
the output voltage can effectively be level shifted in a
VID7
1
1
1
1
VID6
0
0
0
0
VID5
1
1
1
1
VID4
0
0
0
0
VID3
0
1
1
1
VID2
1
0
0
0
VID1
1
0
0
1
VID0
1
0
1
0
VDAC
0.56875
0.56250
0.55625
0.55000
direction which works to achieve the load line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that
results from fast load current demand changes.
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
0.54375
0.53750
0.53125
EXTERNAL CIRCUIT
COMP
ISL6333 INTERNAL CIRCUIT
VID DAC
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0.52500
0.51875
0.51250
C C
REF
1k
1
0
1
1
0
0
0
1
0.50625
R C
C REF
ERROR
+
1
0
1
1
0
0
1
0
0.50000
FB
AMPLIFIER
-
V COMP
1
1
1
1
1
1
1
0
OFF
I OFS
1
1
1
1
1
1
1
1
OFF
IDROOP
I AVG
Voltage Regulation
The integrating compensation network shown in Figure 7,
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
R FB
+
(V DROOP + V OFS )
-
VDIFF
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the controllers to include the
combined tolerances of each of these elements.
V OUT +
V OUT -
VSEN
RGND
+
-
DIFFERENTIAL
The output of the error amplifier, V COMP , is compared to the
modulator waveform to generate the PWM signals. The
PWM signals control the timing of the Internal MOSFET
drivers and regulate the converter output so that the voltage
at FB is equal to the voltage at REF. This will regulate the
output voltage to be equal to Equation 8. The internal and
external circuitry that controls voltage regulation is illustrated
in Figure 7.
REMOTE-SENSE
AMPLIFIER
FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
V OUT = V REF – V OFS – V DROOP
(EQ. 8)
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
V OUT = V REF – V OFS – ? ------------- ? --------------- ? ---------- ? R FB ?
? N
?
R SET
3
The controllers incorporate an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote sense output, V DIFF , is
connected to the inverting input of the error amplifier through
an external resistor.
Load Line (Droop) Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
24
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 7, a current proportional to the average
current of all active channels, I AVG , flows from the IDROOP pin
through a load line regulation resistor R FB . The resulting
voltage drop across R FB is proportional to the output current,
effectively creating an output voltage droop with a steady-state
value defined as Equation 9:
V DROOP = I AVG ? R FB (EQ. 9)
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equations 6, 7, 8, and 9.
? I OUT DCR 400 ?
(EQ. 10)
FN6520.3
October 8, 2010
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| ISL6333IRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZR5368 | 功能描述:IC CTRLR PWM 4PHASE BUCK 40QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ-TR5368 | 功能描述:IC CTRLR PWM 4PHASE BUCK 40QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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