参数资料
型号: ISL6333IRZ
厂商: Intersil
文件页数: 27/40页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR11
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6333, ISL6333A, ISL6333B, ISL6333C
.
12.0
EXTERNAL CIRCUIT
ISL6333, ISL6333B INTERNAL CIRCUIT
11.8
+40°C THERMAL
PVCC1
+12V
1.0μF
GVOT
REG.
SET BY STATE
OF PSI# AND
SS PINS
11.6
11.4
11.2
BYP1
11.0
1.0μ F
PVCC2_3
LVCC1
LVCC2, LVCC3
10.8
10.6
+12V
1.0μF
10.4
0
20
40 60 80
AVERAGE LOAD CURRENT (mA)
100
120
+5V TO
PUVCC
UVCC1, UVCC2,
UVCC3
FIGURE 13. BYP1, LVCC1 VOLTAGE WHEN PSI# IS HIGH
+12V
1.0μ F
LVCC = LOWER GATE DRIVE
UVCC = UPPER GATE DRIVE
8.5
+40°C THERMAL
FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND
GAVE VOLTAGE OPTIMIZATION (GVOT)
Gate Voltage Optimization Technology (GVOT)
(ISL6333, ISL6333B Only)
The ISL6333 and ISL6333B are designed to optimize the
Channel 1 lower MOSFET gate drive voltage to ensure high
efficiency in both normal and low power states. In the normal
8.0
7.5
7.0
6.5
R SS TIED TO VCC
power state when the converter load current is high, the
conduction losses of the lower MOSFETs play a large role in
the overall system efficiency. In normal power state, the
lower gate drive voltage should be higher to decrease the
conduction losses of the lower MOSFETs and increase the
6.0
5.5
5.0
R SS TIED TO GND
system efficiency. In the low power state, where the
0
20
40
60
80
100
120
converter load current is significantly smaller, MOSFET
driving loss becomes a much higher percentage of power
loss associated with the lower MOSFET. In low power state,
the lower gate drive voltage can therefore be reduced to
decrease the driving losses of the lower MOSFETs and
increase the system efficiency.
This gate drive voltage optimization is accomplished by an
internal linear regulator that regulates the Channel 1 lower
gate drive voltage, LVCC1, to certain levels depending on
the state of the PSI# and SS pins. The input and output of
this internal regulator is the PVCC1 pin and BYP1 pin,
respectively. The regulator input, PVCC1, should be
connected to a +12V source and decoupled with a quality
1.0μF ceramic capacitor. The regulator output, BYP1, is
internally connected to the lower gate drive of the Channel 1
MOSFET driver, LVCC1. The BYP1 pin should also be
decoupled using a quality 1.0μF ceramic capacitor.
27
AVERAGE LOAD CURRENT (mA)
FIGURE 14. BYP1, LVCC1 VOLTAGE WHEN PSI# IS LOW
As Figures 13 and 14 illustrate, the internal regulator has
been designed so that its output voltage, BYP1, is dependent
upon the average load current. In the normal power state,
when PSI# is high, the ISL6333 and ISL6333B regulate BYP1
to around 11.2V at a 50mA average load current. In the low
power state, when PSI# is low, BYP1 is regulated down to one
of two voltages depending on the state of the SS pin. If the SS
pin is tied to ground through the R SS resistor, BYP1 is
regulated down to 5.75V at a 50mA average load current. If
the SS pin is tied to VCC through the R SS resistor, BYP1 is
regulated down to 7.75V at a 50mA average load current.
It is possible to disable the internal GVOT regulator by shorting
the PVCC1 pin to the BYP1 pin. This essentially bypasses the
internal regulator setting the Channel 1 lower gate drive
voltage, LVCC1, to the voltage input on the PVCC1 pin.
FN6520.3
October 8, 2010
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