参数资料
| 型号： | ISL6333IRZ |
| 厂商： | Intersil |
| 文件页数： | 32/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6333, ISL6333A, ISL6333B, ISL6333C
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t 1 and the
When designing the controllers into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
I P-P
I M
P UP ( 1 ) ≈ V IN ? ? ------ + ---------- ? ? ? ---- 1 ? ? f S
? t ?
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
approximated associated power loss is P UP(1) .
(EQ. 26)
? N 2 ? ? 2 ?
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 27, the
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
(EQ. 30)
P UP ( 2 ) ≈ V IN ? ? ------ – ---------- ? ? ? ---- 2 ? ? f S
I DR = ? --- ? Q G1 ? N + Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
approximate power loss is P UP(2) .
? I M I P-P ? ? t ?
? N 2 ? ? 2 ?
A third component involves the lower MOSFET
(EQ. 27)
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
3
? 2 Q1 ?
(EQ. 31)
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP(3) shown in Equation 28.
In Equations 30 and 31, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
P UP ( 3 ) = V IN ? Q rr ? f S
(EQ. 28)
quiescent current with no load at both drive outputs; N Q1 and
N Q2 are the number of upper and lower MOSFETs per phase,
I P-P2
? I M ?
P UP ( 4 ) ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as P UP(4). .
2
(EQ. 29)
? N ? 12
The total power dissipated by the upper MOSFET at full load
respectively; N PHASE is the number of active phases. The
I Q *VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
PVCC BOOT
D
C GD
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
equations depend on MOSFET parameters, choosing the
R HI1
R LO1
UGATE
G
R G1
R GI1
C DS
correct MOSFETs can be an iterative process involving
C GS
Q 1
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controllers. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
S
PHASE
FIGURE 20. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
R HI2
R LO2
LGATE
G
R G2
R GI2
C GS
S
C DS
Q 2
dissipation for the 7x7 QFN package is approximately 3.5W
32
FIGURE 21. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FN6520.3
October 8, 2010
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| ISL6333IRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZR5368 | 功能描述:IC CTRLR PWM 4PHASE BUCK 40QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334ACRZ-TR5368 | 功能描述:IC CTRLR PWM 4PHASE BUCK 40QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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