参数资料
型号: ISL6334ACRZ-TR5368
厂商: Intersil
文件页数: 29/31页
文件大小: 0K
描述: IC CTRLR PWM 4PHASE BUCK 40QFN
标准包装: 4,000
应用: 控制器,Intel VR11.1
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
ISL6334AR5368
0.3
I L(P-P) = 0
I L(P-P) = 0.25 I O
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
MULTIPHASE RMS IMPROVEMENT
Figure 21 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
0.2
0.1
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of I L,PP to I O of 0.5. The
single phase converter would require 17.3A RMS current
capacity while the two-phase converter would only require
10.9A RMS . The advantages become even more pronounced
when output current is increased and additional phases are
0
0
0.2
0.4 0.6
DUTY CYCLE (V O/ V IN )
0.8
1.0
added to keep the component cost down relative to the
single phase approach.
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
0.6
0.3
I L(P-P) = 0
I L(P-P) = 0.25 I O
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
0.4
0.2
0.2
I L(P-P) = 0
I L(P-P) = 0.5 I O
0.1
I L(P-P) = 0.75 I O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V O/ V IN )
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS
0
0
0.2
0.4 0.6
DUTY CYCLE (V O/ V IN )
0.8
1.0
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a 2-phase design, use Figure 18 to determine the input-
capacitor RMS current requirement given the duty cycle,
maximum sustained output current (I O ), and the ratio of the
per-phase peak-to-peak inductor current (I L(P-P) ) to I O .
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage.
Figures 19 and 20 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as previously described.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
29
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same placement
of these components for each phase.
FN6839.2
September 7, 2010
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