参数资料
型号: ISL6336AIRZ
厂商: Intersil
文件页数: 15/31页
文件大小: 0K
描述: IC CTRLR PWM 6PHASE BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR11.1
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6336, ISL6336A
L
.
L
I
R SENSE V OUT
C OUT
output, V DIFF , is connected to the inverting input of the error
amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
ISL6336, ISL6336A
INTERNAL CIRCUIT
through VID0. The DAC decodes the 8-bit logic signal (VID)
I n
R ISEN(n)
into one of the discrete voltages shown in Table 3. Each VID
input has an internal 30μA minimum pull-up to VCC after
t D3 . The pull-up current diminishes to zero above the logic
CURRENT
SENSE
+
-
ISEN-(n)
ISEN+(n)
C T
threshold (near 1V) to protect voltage-sensitive output
devices. External pull-up resistors can augment the pull-up
current sources in case the leakage into the driving device is
greater than 30μA.
I
R
R SENSE
SEN = I L --------------------------
ISEN
EXTERNAL CIRCUIT
R C C C
COMP
ISL6336, ISL6336A
INTERNAL CIRCUIT
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
DAC
Channel-Current Balance
The sensed current I n from each active channel are summed
together and divided by the number of active channels. The
R REF
C REF
REF
+
resulting average current I AVG provides a measure of the
FB
-
V COMP
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
R FB
+
V DROOP
-
VDIFF
IAVG
ERROR AMPLIFIER
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
V OUT +
V OUT -
VSEN
RGND
+
-
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 6 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
TABLE 3. VR11 VID 8-BIT
error amplifiers. Intersil specifies the guaranteed tolerance of
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0 VOLTAGE
the ISL6336, ISL6336A to include the combined tolerances
of each of these elements.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitries which
control the voltage regulation are illustrated in Figure 6 .
The ISL6336, ISL6336A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF
OFF
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
15
FN6504.1
May 28, 2009
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