参数资料
| 型号： | ISL6336AIRZ |
| 厂商： | Intersil |
| 文件页数： | 18/31页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 6PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
ISL6336, ISL6336A
TABLE 3. VR11 VID 8-BIT (Continued)
the ISEN+ pin, and R FB is the feedback resistor, N is the
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0 VOLTAGE
active channel number, and R X is the DCR, or R SENSE
1
1
0
0
1
1
0
0
1
1
1
1
0
1
1
0
0.53125
0.52500
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
R LL = ------------ ? ------------------
R ISEN
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
0.51875
0.51250
R FB R X
N
(EQ. 10)
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
0
1
0.50625
0.50000
OFF
OFF
Output-Voltage Offset Programming
The ISL6336, ISL6336A allows the designer to accurately
adjust the offset voltage. When resistor, R OFS , is connected
between OFS to VCC, the voltage across it is regulated to
1.6V. This causes a proportional current (I OFS ) to flow into
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a direction
which works to achieve the load-line regulation required by
OFS. If R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set R OFS :
R OFS = ----------------------------
R OFS = ----------------------------
these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
For Positive Offset (connect R OFS to VCC):
1.6 ? R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 ? R REF
V OFFSET
FB
DYNAMIC
(EQ. 11)
(EQ. 12)
DAC
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined in Equation 8.
E/A
VID D/A
R REF
REF
C REF
V DROOP = I AVG ? R FB
(EQ. 8)
VCC
OR
GND
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
1.6V
-
+
0.4V
+
-
ISL6336, ISL6336A
OFS
R OFS
V OUT = V REF – V OFS – ? ------------- ? ------------------ ? R FB ?
? ?
R ISEN
? I OUT R X ?
N
(EQ. 9)
VCC GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor connected to
18
FN6504.1
May 28, 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6336AIRZ-T | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336BCRZ | 功能描述:IC CTRLR PWM SYNC BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6336BCRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336BIRZ | 功能描述:IC CTRLR PWM SYNC BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6336BIRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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