参数资料
| 型号： | ISL6363IRTZ |
| 厂商： | Intersil |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER VR12 48TQFN |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VR12 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 管件 |
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ISL6363
eliminate the effect of phase node parasitic PCB DCR.
FB
Rdroop
Vdroop
Idroop
VCC SENSE
VR LOCAL VO
“CATCH”
RESISTOR
Equations 5 through 7 give the ISEN pin voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
V ISEN3 = ( R dcr3 + R pcb3 ) × I L3
(EQ. 5)
(EQ. 6)
(EQ. 7)
Σ VDAC DAC VID
X1
VSS
V droop = R droop × I droop
Rpcb2
TO IC
Rpcb1
E/A
COMP
RTN
VSS SENSE
INTERNAL
TO IC
“CATCH”
RESISTOR
FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
I droop flows through resistor R droop and creates a voltage drop as
shown in Equation 2.
(EQ. 2)
V droop is the droop voltage required to implement load line.
Changing R droop or scaling I droop can both change the load line
slope. Since I droop also sets the overcurrent protection level, it is
recommended to first scale I droop based on OCP requirement,
then select an appropriate R droop value to obtain the desired
load line slope.
Differential Voltage Sensing
Figure 9 also shows the differential voltage sensing scheme.
VCC SENSE and VSS SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS SENSE voltage and add it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
Where R dcr1 , R dcr2 and R dcr3 are inductor DCR; R pcb1 , R pcb2
and R pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I L1 , I L2 and I L3 are
inductor average currents.
L3 Rdcr3
Rpcb3
Phase3
Risen
ISEN3 IL3
Cisen
L2 Rdcr2
INTERNAL Vo
Phase2
Risen
ISEN2 IL2
Cisen
L1 Rdcr1
Phase1
Risen
ISEN1 IL1
Cisen
FIGURE 10. CURRENT BALANCING CIRCUIT
The ISL6363 will adjust the phase pulse-width relative to the
other phases to make V ISEN1 = V ISEN2 = V ISEN3 , thus, to achieve
I L1 = I L2 = I L3 , when there are R dcr1 = R dcr2 = R dcr3 and
R pcb1 = R pcb2 = R pcb3 .
Using the same components for L1, L2 and L3 will provide a good
match of R dcr1 , R dcr2 and R dcr3 . Board layout will determine
R pcb1 , R pcb2 and R pcb3 . It is recommended to have symmetrical
layout for the power delivery path between each inductor and the
output voltage rail, such that R pcb1 = R pcb2 = R pcb3 .
V3n
VCC SENSE + V droop = V DAC + VSS SENSE
Rewriting Equation 3 and substitution of Equation 2 gives
(EQ. 3)
ISEN3
Cisen
Phase3
Risen
Risen
V3p
L3
Rdcr3
IL3
Rpcb3
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
V2n
V1n
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCC SENSE and VSS SENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 9 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10 Ω ~100 Ω , will provide voltage
INTERNAL
TO IC
ISEN2
Cisen
ISEN1
Cisen
Risen
V2p
Phase2
Risen
Risen
Risen
V1p
Phase1
Risen
Risen
L2
L1
Rdcr2
IL2
Rdcr1
IL1
Rpcb2
Rpcb1
Vo
feedback if the system is powered up without a processor installed.
Phase Current Balancing
The ISL6363 monitors individual phase average current by
monitoring the ISEN1, ISEN2, ISEN3, and ISEN4 voltages.
Figure 10 shows the current balancing circuit recommended for
ISL6363 for a 3-Phase configuration as an example. Each phase
node voltage is averaged by a low-pass filter consisting of R isen
and C isen , and presented to the corresponding ISEN pin. R isen
should be routed to the inductor phase-node pad in order to
17
Risen
FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes it is difficult to implement symmetrical layout. For
the circuit shown in Figure 10, asymmetric layout causes
different R pcb1 , R pcb2 and R pcb3 , thus current imbalance.
Figure 11 shows a differential-sensing current balancing circuit
recommended for the ISL6363. The current sensing traces
should be routed to the inductor pads so they only pick up the
inductor DCR voltage. Each ISEN pin sees the average voltage of
FN6898.1
September 5, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6363IRTZ-T | 功能描述:IC CONTROLLER VR12 48TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6364ACRZ | 功能描述:IC CNTRLR DUAL IMVP7 VR12 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6364ACRZ-T | 功能描述:IC CNTRLR DUAL IMVP7 VR12 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6364AIRZ | 功能描述:IC CNTRLR DUAL IMVP7 VR12 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6364AIRZ-T | 功能描述:IC CNTRLR DUAL IMVP7 VR12 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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