参数资料
型号: ISL6363IRTZ
厂商: Intersil
文件页数: 20/32页
文件大小: 0K
描述: IC CONTROLLER VR12 48TQFN
标准包装: 50
应用: 控制器,Intel VR12
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 0.25 V ~ 1.52 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
ISL6363
VR_HOT#/ALERT# Behavior
5. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register bit 6 flipping.
Temp Zone
Bit 7 =1
Bit 6 =1
1
VR Temperature
7
3% Hysteresis
10
1111 1111
0111 1111
6. The controller clears ALERT#.
7. The temperature continues rising.
8. The temperature crosses the threshold where the TZONE
Bit 5 =1
12
0011 1111
0001 1111
register Bit 7 changes from 0 to 1.
9. The controller asserts the VR_HOT# signal. The CPU throttles
Temp Zone
Register
2
8
back and the system temperature starts dropping eventually.
10. The temperature crosses the threshold where the TZONE
5
15
0001 1111 0011 1111
Status 1
Register = “001”
0 1 11 1111
3
= “0 1 1”
GerReg
1 111 1111
0 1 11 1111
0011 1111
13
0001 1111
= “0 0 1”
GerReg
register bit 6 changes from 1 to 0. This threshold is 1 ADC step
lower than the one when VR_HOT# gets asserted, to provide
3% hysteresis.
SVID
Status1
Status1
11. The controllers de-assert the VR_HOT# signal.
ALERT#
VR_HOT#
4
6
9
11
14
16
12. The temperature crosses the threshold where the TZONE
register bit 5 changes from 1 to 0. This threshold is 1 ADC step
lower than the one when ALERT# gets asserted during the
temperature rise to provide 3% hysteresis.
FIGURE 14. VR_HOT#/ALERT# BEHAVIOR
The controller drives 60μA current source out of the NTC pin and
the NTCG pin alternatively at 1kHz frequency with 50% duty
cycle. The current source flows through the respective NTC
resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter (ADC) to
generate the TZONE value. Table 4 shows the programming table
for TZONE. The user needs to scale the NTC and the NTCG
network resistance such that it generates the NTC (and NTCG) pin
voltage that corresponds to the left-most column. Do not use any
capacitor to filter the voltage.
TABLE 4. TZONE TABLE
13. The controller changes Status_1 register bit 1 from 1 to 0.
14. The controller asserts ALERT#.
15. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register bit 5 flipping.
16. The controller clears ALERT#.
Protection Functions
VR1 and VR2 both provide overcurrent, current-balance and
overvoltage fault protections. The controller also provides
over-temperature protection. The following discussion is based on
VR1 and also applies to VR2.
The controller determines overcurrent protection (OCP) by
VNTC (V)
0.84
0.88
0.92
0.96
1.00
1.04
1.08
1.12
1.16
1.2
TMAX (%)
>100
100
97
94
91
88
85
82
79
76
TZONE
FFh
FFh
7Fh
3Fh
1Fh
0Fh
07h
03h
01h
01h
comparing the average value of the droop current I droop with an
internal current source threshold as Table 2 shows. It declares
OCP when I droop is above the threshold for 120μs.
For overcurrent conditions above 1.5x the OCP level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as
way-overcurrent protection or fast-overcurrent protection, for
short-circuit protections.
The controller monitors the ISEN pin voltages to determine
current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
The controller takes the same actions for all of the above fault
>1.2 <76 00h
Figure 14 shows how the NTC and the NTCG network should be
designed to get correct VR_HOT#/ALERT# behavior when the
system temperature rises and falls, manifested as the NTC and the
NTCG pin voltage falls and rises. The series of events are:
1. The temperature rises so the NTC pin (or the NTCG pin)
voltage drops. TZONE value changes accordingly.
2. The temperature crosses the threshold where the TZONE
register Bit 6 changes from 0 to 1.
3. The controller changes Status_1 register bit 1 from 0 to 1.
4. The controller asserts ALERT#.
20
protections: de-assertion of PGOOD and turn-off of the high-side
and low-side power MOSFETs. Any residual inductor current will
decay through the MOSFET body diodes.
The controller will declare an overvoltage fault and de-assert PGOOD
if the output voltage exceeds the VID set value by +200mV. The
ISL6363 will immediately declare an OV fault, de-assert PGOOD,
and turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled down below
the VID set value when all power MOSFETs are turned off. If the
output voltage rises above the VID set value +200mV again, the
protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground.
FN6898.1
September 5, 2013
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