参数资料
型号: ISL6363IRTZ
厂商: Intersil
文件页数: 23/32页
文件大小: 0K
描述: IC CONTROLLER VR12 48TQFN
标准包装: 50
应用: 控制器,Intel VR12
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 0.25 V ~ 1.52 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
ISL6363
V Cn ( s ) = ? ----------------------------------------- × ------------ ? × I o ( s ) × A cs ( s )
R sum
N ?
?
R ntcs + R ntc + R p
1 + ------
A cs ( s ) = ----------------------
ω L
1 + ------------
ω L = ------------
L
(EQ. 24)
C n = ------------------------------------------------------------
R ntcnet × --------------
----------------------------------------- × DCR
current-sensing summing network. It is recommended to use
1 Ω ~10 Ω R o to create quality signals. Since R o value is much
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.
The summed inductor current information is presented to the
capacitor C n . Equations 19 thru 23 describe the
frequency-domain relationship between inductor total current
I o (s) and C n voltage V Cn (s):
? ?
? R ntcnet DCR ?
(EQ. 19)
N
? R ntcnet + -------------- ?
( R ntcs + R ntc ) × R p
R ntcnet = --------------------------------------------------- (EQ. 20)
s
(EQ. 21)
s
ω sns
DCR
(EQ. 22)
and solving for the solution, Equation 24 gives Cn value.
L
R sum
N
N
R sum
R ntcnet + --------------
For example, given N = 3, R sum = 3.65k Ω , R p = 11k Ω ,
R ntcs = 2.61k Ω , R ntc = 10k Ω , DCR = 0.88m Ω and L = 0.36μH,
Equation 24 gives C n = 0.406μF.
Assuming the compensator design is correct, Figure 17 shows the
expected load transient response waveforms if C n is correctly
selected. When the load current I core has a square change, the
output voltage V CORE also has a square response.
If C n value is too large or too small, V Cn (s) will not accurately
represent real-time I o (s) and will worsen the transient response.
Figure 18 shows the load transient response when C n is too
small. V CORE will sag excessively upon load insertion and may
create a system failure. Figure 19 shows the transient response
when C n is too large. V CORE is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
ω sns = ------------------------------------------------------
R ntcnet × --------------
----------------------------------------- × C n
1
R sum
N
N
R sum
R ntcnet + --------------
Where N is the number of phases.
(EQ. 23)
I O
Transfer function A cs (s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R ntc
values decreases as its temperature decreases. Proper
selections of R sum , R ntcs , R p and R ntc parameters ensure that
V Cn represent the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the R sum resistors form a voltage divider, V cn is always a
fraction of the inductor DCR voltage. It is recommended to have a
higher ratio of V cn to the inductor DCR voltage, so the droop circuit
has higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R sum = 3.65k Ω , R p = 11k Ω , R ntcs = 2.61k Ω and
R ntc = 10k Ω (ERT-J1VR103J). The NTC network parameters may
need to be fine tuned on actual boards. One can apply full load DC
current and record the output voltage reading immediately; then
record the output voltage reading again when the board has
reached the thermal steady state. A good NTC network can limit the
output voltage drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing network
parameters to minimize engineering time.
V Cn (s) also needs to represent real-time I o (s) for the controller to
achieve good transient response. Transfer function A cs (s) has a
pole w sns and a zero w L . One needs to match w L and w sns so
A cs (s) is unity gain at all frequencies. By forcing w L equal to w sns
23
VO
FIGURE 17. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
I O
VO
FIGURE 18. LOAD TRANSIENT RESPONSE WHEN C n IS TOO SMALL
I O
VO
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C n IS TOO LARGE
FN6898.1
September 5, 2013
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