参数资料
型号: ISL6363IRTZ
厂商: Intersil
文件页数: 29/32页
文件大小: 0K
描述: IC CONTROLLER VR12 48TQFN
标准包装: 50
应用: 控制器,Intel VR12
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 0.25 V ~ 1.52 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
ISL6363
NTC Network on the NTC and the NTCG pins
The controller drives 60μA current source out of the NTC pin and
the NTCG pin alternatively at 1kHz frequency with 50% duty
cycle. The current source flows through the respective NTC
resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter to generate
the TZONE value. Table 10 shows the programming table for
TZONE. The user needs to scale the NTC (and NTCG) network
resistance such that it generates the NTC (and NTCG) pin voltage
that corresponds to the left-most column. Do not use any
capacitor to filter the voltage. On ADC Output = 7, the controller
issues thermal alert to the CPU, on ADC Output <7, the controller
asserts the VR_HOT# signal.
TABLE 10. TZONE PROGRAMMING TABLE
VNTC (V) ADC OUTPUT %TMAX TZONE
0.64 0 >100% FFh
0.68 1 >100% FFh
0.72 2 >100% FFh
For example, given LL = 1.9m Ω , R droop = 2.825k Ω ,
V Rimon = 2.7V at I omax = 53A, Equation 42 gives
R imon = 25.2k Ω .
A capacitor C imon can be paralleled with R imon to filter the IMON
pin voltage. The R imon C imon time constant is the user’s choice. It
is recommended to have a time constant long enough such that
switching frequency ripples are removed.
Current Balancing
The ISL6363 achieves current balancing through matching the
ISEN pin voltages. R isen and C isen form filters to remove the
switching ripple of the phase node voltages. It is recommended
to use a rather long R isen C isen time constant such that the ISEN
voltages have minimal ripple and represent the DC current
flowing through the inductors. Recommended values are
R s = 10k Ω and C s = 0.22μF.
Optional Slew Rate Compensation Circuit for
1-Tick VID Transition
0.76
3
>100%
FFh
0.80
0.84
0.88
4
5
6
>100%
>100%
100%
FFh
FFh
FFh
Rdroop
Rvid Cvid
Vcore
OPTIONAL
0.92
0.96
1.00
7
8
9
97%
94%
91%
7Fh
3Fh
1Fh
FB
Ivid
Idroop_vid
1.04
1.08
1.12
1.16
A
B
C
D
88%
85%
82%
79%
0Fh
07h
03h
01h
COMP
E/A
INTERNAL
Σ VDAC DAC
X1
VIDs
RTN
VSS
VID<0:6>
VSSSENSE
1.2
>1.2
E
F
76%
<76%
01h
00h
TO IC
VID<0:6>
Current Monitor
Refer to Equation 18 for the IMON pin current expression.
Referencing the “Simplified Application Circuit” on page 6, the
IMON pin current flows through R imon . The voltage across R imon is
expressed in Equation 39:
Vfb
Ivid
V Rimon = 3 × I droop × R imon
Rewriting Equation 38 gives Equation 40:
(EQ. 39)
Vcore
I droop = ------------------ × LL
I o
R droop
(EQ. 40)
Idroop_vid
Substitution of Equation 40 into Equation 39 gives Equation 41:
3I o × LL
V Rimon = --------------------- × R imon
R droop
(EQ. 41)
FIGURE 27. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR
1-TICK VID TRANSITION
3I o × LL
Rewriting Equation 41 and application of full load condition gives
Equation 42:
V Rimon × R droop
R imon = -------------------------------------------- (EQ. 42)
29
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(5mV) per 0.5μs, controlling output voltage V CORE slew rate at
10mV/μs.
FN6898.1
September 5, 2013
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