参数资料
| 型号： | ISL6540AIRZA-T |
| 厂商： | Intersil |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 28-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 100% |
| 电源电压： | 2.97 V ~ 22 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6540AIRZA-TDKR |
ISL6540A
C 2
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F 0dB and 180°.
COMP
R 2
E/A
-
+
C 1
FB
R 3
R 1
C 3
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 ,
and C 3 ) in Figures 7 and 9. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 10k Ω , typically). Calculate
VREF
value for R 2 for desired converter bandwidth (F 0 ). If
VMON
R FB
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
-
+
VSEN-
VSEN+
C SEN
R OS
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 9), in order
to compensate for the attenuation introduced by the
PWM
OSCILLATOR
V OSC
V IN
V OUT
resistor divider, the below obtained R 2 value needs be
multiplied by a factor of (R OS +R FB )/R OS . The remainder
of the calculations remain unchanged, as long as the
compensated R 2 value is used.
d MAX ? V IN ? F LC
CIRCUIT
HALF-BRIDGE
UGATE
L
DCR
V OSC ? R 1 ? F 0
R 2 = ---------------------------------------------
(EQ. 11)
DRIVE
PHASE
LGATE
C
ESR
A small capacitor, C SEN in Figure 9, can be added to filter
out noise, typically C SEN is chosen so the corresponding
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
frequency of the regulator. As the ISL6540A supports
ISL6540A
EXTERNAL CIRCUIT
100% duty cycle, d MAX equals 1. The ISL6540A also
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
uses feedforward compensation, as such V OSC is equal
to 0.16 multiplied by the voltage at the VFF pin. When
tieing VFF to V IN , the Equation 12 simplifies to:
R 2 = ----------------------------------
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
0.16 ? R 1 ? F 0
F LC
(EQ. 12)
(V OUT ) is regulated to the reference voltage, VREF, level.
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a
pulse-width modulated wave with an amplitude of V IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
C 1 = -----------------------------------------------
2 π ? R 2 ? C 1 ? F CE – 1
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a
DC gain, given by D MAX V IN /V OSC , and shaped by the
output filter, with a double pole break frequency at F LC and a
zero at F CE . For the purpose of this analysis C and ESR
represent the total output capacitance and its equivalent
1
2 π ? R 2 ? 0.5 ? F LC
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 13)
(EQ. 14)
F LC = ---------------------------
F CE = ---------------------------------
series resistance.
1
2 π ? L ? C
1
2 π ? C ? ESR
(EQ. 10)
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below F SW (typically, 0.5 to 1.0
times F SW ). F SW represents the regulator’s switching
The compensation network consists of the error amplifier
(internal to the ISL6540A) and the external R 1 thru R 3 , C 1 thru
C 3 components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
18
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F P2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
FN6288.5
October 7, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6540AIRZR5359 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6540AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6540AIRZ-TR5359 | 制造商:Intersil Corporation 功能描述: |
| ISL6540AIRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6540AIRZ-T WITH GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6540CRZ | 制造商:Intersil Corporation 功能描述:VOLT MODE PWM CNTRLR 0.6V TO 20V 30A 28QFN EP - Rail/Tube |
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