参数资料
型号: ISL6557ACB-T
厂商: Intersil
文件页数: 11/18页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-SOIC
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 250kHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
ISL6557A
During the soft-start interval, the soft-start voltage, V RAM P ,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I RAMP , is
decreasing from 160 μ A down to zero. These signals are
connected as shown in Figure 9 (I OUT may or may not be
connected to FB depending on the particular application).
leading to T SS = 4.0ms, t DELAY = 700ns, t RAMP1 = 2.23ms,
and t RAMP2 = 1.17ms.
VOUT, 500mV/DIV
EXTERNAL CIRCUIT
ISL6557A INTERNAL CIRCUIT
R C
C C
COMP
FB
ERROR AMPLIFIER
-
R FB
IOUT
+
V COMP
EN, 5V/DIV
REFERENCE
VOLTAGE
VDIFF
I RAMP
t DELAY t RAMP1
t RAMP2
I AVG
V RAMP
1ms/DIV
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6557A
IDEAL DIODES
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
The ideal diodes in Figure 9 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V RAM P . Since I RAMP creates an initial offset
across R FB of R FB times 160 μ A, the first PWM pulses will
not be seen until V RAMP is greater than the R F B I RAMP
offset. This produces a delay after the ISL6557A enables
before the output voltage starts moving. For example, if
VID = 1.5V, R FB = 1k Ω and T SS = 8.3ms, the delay time
can be expressed using Equation 6.
BASED MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and R FB = 2.67k Ω
DYNAMIC VID
The ISL6557A is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation ), the
ISL6557A checks for a change in the VID code. The VID
code is the bit pattern present at pins VID4-VID0 as outlined
in Voltage Regulation . If the new code remains stable for
another full cycle, the ISL6557A begins incrementing the
reference by making 25mV change every two switching
cycles until the it reaches the new VID code.
t DELAY = --------------------------------------------------- = 580 μ s
1 + ---------------------------------------- 6 -
T SS
1.4 ( VID )
R FB 160 × 10 –
(EQ. 6)
01110
00010
V ID , 5V/DIV
VID CHANGE OCCURS
ANYWHERE HERE
From this point, the soft start ramps linearly until V RAMP
reaches VID. For the system described above, this first
linear ramp will continue for approximately
1.3V
V REF , 100mV/DIV
T SS
t RAMP1 = ----------- – t DELAY
1.4
= 5.27ms
(EQ. 7)
1.3V
V OUT , 100mV/DIV
The final portion of the soft-start sequence is the time
remaining after V RAMP reaches VID and before I RAMP gets to
zero. This is also characterized by a slight linear ramp in the
output voltage which, for the current example, exists for a time
5 μ s/DIV
FIGURE 11. DYNAMIC-VID WAVEFORMS FOR 500KHZ
t RAMP2 = T SS – t RAMP1 – t DELAY
(EQ. 8)
ISL6557A BASED MULTI-PHASE BUCK
CONVERTER
= 2.34ms
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, R FB is set to 2.67k Ω
Since the ISL6557A recognizes VID-code changes only at
the beginnings of switching cycles, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
Thus, the total time required for a VID change, t DV , is
11
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