参数资料
| 型号： | ISL6557ACB-T |
| 厂商： | Intersil |
| 文件页数： | 13/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-SOIC |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
ISL6557A
Finally, the resistive part of the upper MOSFET’s is given in
Equation 15 as P UP,4 .
ISEN resistor, the load-line regulation resistor is as shown
in Equation 18.
I PP2
? I M ?
P UP , 4 = r DS ( ON ) ? ------ ? d + ----------
2
? N ? 12
(EQ. 15)
– 6
V DROOP
R FB = -------------------------
50 × 10
(EQ. 18)
∑ R ISEN ( n )
V DROOP
R FB = --------------------------------
r DS ( ON ) I FL
R ISEN = -----------------------
50 × 10 – 6
In this case, of course, r DS(ON) is the on resistance of the
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 12, 13, 14 and 15. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
and different switching frequencies until converging upon the
best solution.
Current Sensing
Pins 18, 15, 14 and 19 are the ISEN pins denoted ISEN1,
ISEN2, ISEN3 and ISEN4 respectively. The resistors
connected between these pins and the phase nodes
determine the gains in the load-line regulation loop and the
channel-current balance loop. Select the values for these
resistors based on the room temperature r DS(ON) of the
lower MOSFETs; the full-load operating current, I FL ; and the
number of phases, N according to Equation 16 (see also
Figure 4).
-------- (EQ. 16)
N
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance ). In these cases, chose new, smaller values of R ISEN
for the affected phases. Choose R ISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
If one or more of the ISEN resistors was adjusted for thermal
balance as in Equation 17, the load-line regulation resistor
should be selected according to Equation19 where I FL is the
full-load operating current and R ISEN(n) is the ISEN resistor
connected to the n th ISEN pin.
(EQ. 19)
I FL r DS ( ON ) n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation , there are two distinct
methods for achieving these goals.
COMPENSATING A LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
Δ T 1
Δ T 2
R ISEN , 2 = R ISEN ----------
(EQ. 17)
C 2 (OPTIONAL)
In Equation 17, make sure that Δ T 2 is the desired temperature
rise above the ambient temperature, and Δ T 1 is the measured
temperature rise above the ambient temperature. While a
R C
C C
COMP
FB
single adjustment according to Equation 17 is usually
sufficient, it may occasionally be necessary to adjust R ISEN
two or more times to achieve perfect thermal balance
R FB
+
V DROOP
IOUT
ISL6557A
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R FB in Figure 7.
Its value depends on the desired full-load droop voltage
(V DROOP in Figure 7). If Equation 16 is used to select each
-
VDIFF
FIGURE 12. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6557A CIRCUIT
13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6557ACBZ | 功能描述:IC REG CTRLR BUCK PWM VM 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6557ACBZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6557CB | 制造商:Intersil Corporation 功能描述: |
| ISL6557CB-T | 制造商:Intersil Corporation 功能描述: |
| ISL6557CB-T WAF | 制造商:Intersil Corporation 功能描述: |
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