参数资料
型号: ISL6557ACB-T
厂商: Intersil
文件页数: 14/18页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-SOIC
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 250kHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
ISL6557A
The feedback resistor, R FB , has already been chosen as out-
lined in Load-Line Regulation Resistor . Select a target band-
width for the compensated system, f 0 . The target bandwidth
must be large enough to assure adequate transient perfor-
mance, but smaller than 1/3 of the per-channel switching fre-
quency. The values of the compensation components
depend on the relationships of f 0 to the L-C pole frequency
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 13, provides the necessary
compensation.
C 2
and the ESR zero frequency. For each of the three cases
defined below, there is a separate set of equations for the
R C
C C
COMP
compensation components.
FB
------------------- > f 0
0.75V IN
2 π V PP R FB f 0
Case 1:
1
2 π LC
2 π f 0 V pp LC
R C = R FB ------------------------------------
0.75V IN
C C = ------------------------------------
C 1
R 1
R FB
+
V DROOP
-
IOUT
VDIFF
------------------- ≤ f 0 < ------------------------------
Case 2:
1 1
2 π LC 2 π C ( ESR )
FIGURE 13. COMPENSATION CIRCUIT FOR ISL6557A BASED
CONVERTER WITHOUT LOAD-LINE
C C = -------------------------------------------------------------
PP R FB LC
( 2 π ) 2 f 2 V
f 0 > ------------------------------
0.75 V IN ( ESR )
2 π V PP R FB f 0 L
Case 3:
V PP ( 2 π ) 2 f 02 LC
0.75 V
R C = R FB --------------------------------------------
IN
0.75V IN
0
1
2 π C ( ESR )
2 π f 0 V pp L
R C = R FB ------------------------------------------
0.75V IN ( ESR ) C
C C = -------------------------------------------------
(EQ. 20)
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general r u le is to chose f HF = 1 0 f 0 , but it can be higher
if desired. Choosing f HF to be lower than 1 0 f 0 can cause
problems with too much phase shift below the system
bandwidth.
R 1 = R FB -----------------------------------------
C 1 = -----------------------------------------
In Equations 20, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V PP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 5 and Electrical Specifications .
Once selected, the compensation values in Equations 20
assure a stable converter with reasonable transient perfor-
mance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equations 21, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equations 21.
C ( ESR )
LC – C ( ESR )
LC – C ( ESR )
R FB
( 2 π ) 2 f 0 f HF LCR FB V PP
? 2 π ? f f
0 HF LC
0.75V IN ? 2 π f HF LC – 1 ?
0.75V IN ? ? 2 π f HF LC – 1 ?
C C = ------------------------------------------------------------------- ?
? 2 π ? 2 V
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equations 20 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 5). Keep
a position available for C 2 , and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
jitter problem is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
14
0.75V IN
C 2 = -------------------------------------------------------------------
2
R FB V PP ? ?
R C = ----------------------------------------------------------------
? ?
? ? PP R FB f 0 f HF LC
(EQ. 21)
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