参数资料
| 型号： | ISL6561CR-T |
| 厂商： | Intersil |
| 文件页数： | 14/26页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM MULTIPHASE 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10X |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 4 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
ISL6561
V COMP
FILTER
+
-
f(j ω )
+
-
SAWTOOTH SIGNAL
PWM1
The ISL6561 incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
I ER
+
-
I AVG
÷ N
Σ
I 4 *
I 3 *
I 2
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through
an external resistor.
I 1
NOTE: *Channels 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Channel current balance is essential in realizing the thermal
advantage of multi-phase operation. The heat generated in
down converting is dissipated over multiple devices and a
greater area. The designer avoids the complexity of driving
multiple parallel MOSFETs, and the expense of using heat
sinks and nonstandard magnetic materials.
Voltage Regulation
The integrating compensation network shown in Figure 7
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6561 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to generate the PWM signals. The PWM
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID12.5. The DAC decodes the a 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 50 μ A pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources in case leakage
into the driving device is greater than 50 μ A.
Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 7.
VID4
0
0
VID3
1
1
VID2
0
0
VID1
1
0
VID0
0
1
VID12.5
0
1
VDAC
0.8375V
0.8500V
R C C C
EXTERNAL CIRCUIT
COMP
DAC
ISL6561 INTERNAL CIRCUIT
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0.8625V
0.8750V
0.8875V
C REF
R REF
REF
+
0
0
0
0
1
1
1
1
1
1
1
0
0.9000V
0.9125V
FB
-
V COMP
0
0
1
1
0
1
0.9250V
R FB
+
V DROOP
-
IDROOP
VDIFF
I AVG
ERROR AMPLIFIER
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0.9375V
0.9500V
0.9625V
0
0
1
0
0
1
0.975V0
V OUT +
V OUT -
VSEN
RGND
+
-
0
0
0
0
1
0
0
1
0
1
0
1
0.9875V
1.0000V
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADUJUSTMENT
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1.0125V
1.0250v
1.0375V
1.0500V
14
FN9098.5
May 12, 2005
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