参数资料
| 型号： | ISL6561CR-T |
| 厂商： | Intersil |
| 文件页数： | 15/26页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM MULTIPHASE 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10X |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 4 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
ISL6561
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID4
0
0
0
1
1
1
VID3
0
0
0
1
1
1
VID2
0
0
0
1
1
1
VID1
0
0
0
1
1
1
VID0
1
0
0
1
1
0
VID12.5
0
1
0
1
0
1
VDAC
1.0625V
1.0750V
1.0875V
OFF
OFF
1.1000V
VID4
0
0
0
0
0
0
VID3
1
1
1
1
1
1
VID2
1
1
1
0
0
0
VID1
0
0
0
1
1
1
VID0
1
0
0
1
1
0
VID12.5
0
1
0
1
0
1
VDAC
1.5375V
1.5500V
1.5625V
1.5750V
1.5875V
1.600V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.1125V
1.1250V
1.1375V
1.1500V
1.1625V
1.1750V
1.1875V
1.2000V
1.2125V
1.2250V
1.2475V
1.2500V
1.2625V
1.2750V
1.2875V
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to control the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1.3000V
1.3125V
1.3250V
V DROOP = I AVG R FB
(EQ. 8)
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1.3375V
1.3500V
1.3625V
1.3750V
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equations 8 with the appropriate
sample current expression defined by the current sense
method employed.
V OUT = V REF – V OFFSET – ? ------------- ------------------ R FB ?
? R ISEN ?
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1.3875V
1.4000V
1.4125V
? I OUT R X ?
4
(EQ. 9)
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.4250V
1.4375V
1.4500V
1.4625V
1.4750V
1.4875V
1.5000V
1.5125V
1.5250V
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, V OUT is the total output current
of the converter, R ISEN is the sense resistor in the ISEN line,
and R FB is the feedback resistor. R X has a value of DCR,
r DS(ON) , or R SENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6561 allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS and VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I OFS flows out of OFS. A resistor
15
FN9098.5
May 12, 2005
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