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参数资料
| 型号： | ISL6567IRZ-TS2698 |
| 厂商： | Intersil |
| 文件页数： | 14/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6567
ISL6567 POWER-GOOD OPERATION
The open-collector PGOOD output reports on the quality of the
regulated output voltage. Once the ISL6567 is enabled and the
MON pin is above its threshold, PGOOD goes open circuit when
the output enters the power-good window (see the “Electrical
Specifications” table starting on page 5, and stays open for as
long as the output remains within the specified window. The
PGOOD is immediately pulled low if the ISL6567 is disabled by
removal of bias, toggling of the EN pin, or upon encountering of
an overcurrent event; PGOOD is allowed to report the status of
the output as soon as operation is resumed following any of
these events.
V TARGET
VOLTAGE TRACKING AND SEQUENCING
By making creative use of the reference clamps at the SS and
REFTRK pins, and/or the available external reference input, as
well as the functionality of the EN pin, the ISL6567 can
accommodate the full spectrum of tracking and sequencing
options. The following figures offer some implementation
suggestions for a few typical situations.
V TARGET
V OUT
V OUT
+
REFTRK
ISL6567
V REF
EXT CIRCUIT
To V TARGET R
S
+
REFTRK
V REF
ISL6567
EXT CIRCUIT
R P
E/A
+
-
FB
R 1
To V TARGET R
S
VDIFF
R P
E/A
+
-
FB
VSEN
R 1
X1
+
R P
VDIFF
-
RGND
R S
V REF R P
V OUT
R P + R S
+
+
VSEN
------------- = --------------------
-
To V OUT
X1
V OUT R P
V TARGET
R P + R S
+
----------------------- = --------------------
-
RGND
-
To V OUT
FIGURE 13. COINCIDENTAL VOLTAGE TRACKING
Simple ratiometric external voltage tracking, such as that
required by the termination voltage regulator for double data
FIGURE 12. RATIOMETRIC VOLTAGE TRACKING
The MON pin is used in external-reference configurations,
where the reference is controlled by a circuit external to the
ISL6567. As such, the ISL6567 has no way of ‘knowing’ when
the external reference has stabilized to its full value, or is
within a certain percentage of its final value. Thus, the MON
pin’s functionality can be used to indicate when a desired
threshold has been reached (either by monitoring the
reference itself, or the output voltage controlled by the
ISL6567). By default, when operating in external-reference
mode and desiring PGOOD monitoring as shown in this
datasheet, it is recommended the MON is set to trip its
threshold when the output voltage (or reference) reaches 92%
of the final set value, choosing the resistor divider as to
achieve a 2% hysteresis.
When operating in internal-reference mode, the value of the
reference is known to the ISL6567, so the MON pin function
can be bypassed by tying it to V CC potential.
14
rate (DDR) memory can be implemented by feeding a
reference voltage equal to 0.5 of the memory core voltage
(VDDQ) to the reference input of the ISL6567, as shown in
Figure 12. The resistor divider at the REFTRK pin sets the V OUT
level. Select a suitable SS capacitor, such that the SS clamp
does not interfere with the desired ramp-up time or slope of
V OUT .
Coincidental tracking using the internal reference results in a
behavior similar to that presented in Figure 13. The resistor
divider at the input of the differential amplifier sets the output
voltage, V OUT , to the desired regulation level. The same resistor
divider used at the REFTRK pin divides down the voltage to be
tracked, effectively scaling it to the magnitude of the internal
reference. As a result, the output voltage ramps up at the
same rate as the target voltage, its ramp-up leveling off at the
programmed regulation level established by the R S /R P
resistor divider.
FN9243.4
August 9, 2011
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