- 您现在的位置：买卖IC网 > PDF目录15181 > ISL6567IRZ-TS2698 (Intersil)IC REG CTRLR BUCK PWM VM 24-QFN PDF资料下载
参数资料
| 型号： | ISL6567IRZ-TS2698 |
| 厂商： | Intersil |
| 文件页数： | 19/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6567
C2
pin, R O in Figure 24, the design procedure can be followed
as presented. However, when setting the output voltage via
a resistor divider placed at the input of the differential
amplifier, in order to compensate for the attenuation
d MAX ? V IN ? F LC
COMP
R2
E/A
C1
-
+
VREF
FB
R3
Ro
R1
C3
introduced by the resistor divider, the obtained R 2 value
needs be multiplied by a factor of (R P +R S )/R P . The
remainder of the calculations remain unchanged, as long
as the compensated R 2 value is used.
V OSC ? R1 ? F 0 (EQ. 15)
R 2 = -----------------------------------------
-
+
VDIFF
RGND
VSEN
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC , at
0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to desired
number). The higher the quality factor of the output filter
and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
C 1 = ---------------------------------------------
OSCILLATOR
V OUT
1
2 π ? R 2 ? 0.5 ? F LC
(EQ. 16)
C 2 = -----------------------------------------------------
PWM
CIRCUIT
V OSC
V IN
3. Calculate C2 such that F P1 is placed at F CE .
C1
2 π ? R 2 ? C 1 ? F CE – 1
(EQ. 17)
HALF-BRIDGE
DRIVE
UGATE
PHASE
L
D
C
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3 such
that F P2 is placed below F SW (typically, 0.5 to 1.0 times
F SW ). F SW represents the per-channel switching frequency.
Change the numerical factor to reflect desired placement
LGATE
E
of this pole. Placement of F P2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R3 = ---------------------
F SW
F LC
C3 = ------------------------------------------------
ISL6567 EXTERNAL CIRCUIT
FIGURE 24. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN
R1
----------- – 1
1
2 π ? R3 ? 0.7 ? F SW
(EQ. 18)
G MOD ( f ) = --------------------------- ? -------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( E + D ) ? C + s ( f ) ? L ? C
(EQ. 14)
F LC = --------------------------
F CE = ----------------------
G FB ( f ) = --------------------------------------------------- ?
s ( f ) ? R1 ? ( C 1 + C 2 )
? -----------------------------------------------------------------------------------------------------------------------
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? ------------------- ? ?
F P1 = -------------------------------------------
C 1 ? C 2
2 π ? R 2 ? C 1
2 π ? R 2 ? ------------------- (EQ. 20)
F P2 = ------------------------------
F Z2 = ------------------------------------------------
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC gain,
given by d MAX V IN /V OSC , and shaped by the output filter, with a
double pole break frequency at F LC and a zero at F CE . For the
purpose of this analysis, L and D represent the individual
channel inductance and its DCR divided by 2 (equivalent parallel
value of the two output inductors), while C and E represents the
total output capacitance and its equivalent series resistance.
1 1
2 π ? L ? C 2 π ? C ? E
The compensation network consists of the error amplifier
(internal to the ISL6567) and the external R 1 to R 3 , C 1 to C 3
components. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing frequency
(F 0 ; typically 0.1 to 0.3 of F SW ) and adequate phase margin
(better than 45 °). Phase margin is the difference between the
closed loop phase at F 0dB and 180°. The equations that follow
relate the compensation network’s poles, zeros and gain to the
components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in Figure 23. Use the
following guidelines for locating the poles and zeros of the
compensation network:
1. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate
value for R 2 for desired converter bandwidth (F 0 ). If setting
the output voltage via an offset resistor connected to the FB
19
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
d MAX ? V IN 1 + s ( f ) ? E ? C
2
1 + s ( f ) ? R 2 ? C 1
(EQ. 19)
1 + s ( f ) ? ( R1 + R3 ) ? C3
? ? C 1 ? C 2 ? ?
? ? C 1 + C 2 ? ?
G CL ( f ) = G MOD ( f ) ? G FB ( f ) where , s ( f ) = 2 π ? f ? j
COMPENSATION BREAK FREQUENCY EQUATIONS
1 1
F Z1 = ------------------------------
C 1 + C 2
1 1
2 π ? ( R 1 + R 3 ) ? C 3 2 π ? R 3 ? C 3
Figure 25 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
FN9243.4
August 9, 2011
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6567IRZ-T | IC REG CTRLR BUCK PWM VM 24-QFN |
| B41041A6158M | 1500UF 50V 16X35.5 SINGLE END |
| ISL6522IVZ | IC REG CTRLR BST PWM VM 14-TSSOP |
| ASC15DRTN | CONN EDGECARD 30POS .100 DIP SLD |
| H2ABT-10110-S4-ND | JUMPER-H1502TR/A2015S/H1500TR10" |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6568CR | 功能描述:IC CTRLR PWM BUCK 2PHASE 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6568CR-T | 功能描述:IC CTRLR PWM BUCK 2PHASE 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6568CRZ | 制造商:Intersil Corporation 功能描述:CURRENT MODE PWM CNTRLR 0.8375V TO 12V 60A 32QFN EP - Rail/Tube 制造商:Intersil 功能描述:2-PH PWM CNTRLR VRM9 W/2-DRVRS 10 K8 DAC |
| ISL6568CRZA | 制造商:Intersil Corporation 功能描述:CURRENT MODE PWM CNTRLR 0.8375V TO 12V 60A 32QFN EP - Rail/Tube 制造商:Intersil 功能描述:W/ANNEAL 2-PH PWM CNTRLR 2-DRVRS VRM9 |
| ISL6568CRZA-T | 制造商:Intersil Corporation 功能描述:CURRENT MODE PWM CNTRLR 0.8375V TO 12V 60A 32QFN EP - Tape and Reel 制造商:Intersil 功能描述:W/ANNEAL 2-PHS PWM CNTRLR W/2-DRVRS |
发布紧急采购，3分钟左右您将得到回复。