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参数资料
| 型号： | ISL6567IRZ-TS2698 |
| 厂商： | Intersil |
| 文件页数： | 9/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6567
ISL6567
V IN
REFERENCE
OSCILLATOR
UGATE1
COMP
Σ
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
PHASE1
LGATE1
L1
R2
C1
Σ
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
R ISEN1
V OUT
FB
Σ
CURRENT
SENSE
ISEN1
V IN
L2
C OUT
R1
AVERAGE
UGATE2
PHASE2
VDIFF
VSEN
RGND
Σ
CURRENT
SENSE
LGATE2
ISEN2
R ISEN2
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6567 VOLTAGE AND CURRENT CONTROL LOOPS
PGOOD (Pin 21)
This pin represents the output of the on-board power-good
monitor. Thus, the FB pin is monitored and compared against a
window centered around the available reference; an FB voltage
within the window disables the open-collector output, allowing
the external resistor to pull-up PGOOD high. Approximate
pull-down device impedance is 65 Ω .
While operating with an external reference, the power-good
function is enabled once the MON pin amplitude exceeds its
monitored threshold (typically 300mV).
Operation
Figure 2 shows a simplified diagram of the voltage regulation
and current loops. The voltage loop is used to precisely
regulate the output voltage, while the current feedback is used
to balance the output currents, I L1 and I L2 , of the two power
channels.
VOLTAGE LOOP
Feedback from the output voltage is fed via the on-board
differential amplifier and applied via resistor R 1 to the
inverting input of the Error Amplifier. The signal generated by
the error amplifier is summed up with the current correction
error signal and applied to the positive inputs of the PWM
circuit comparators. Out-of-phase sawtooth signals are applied
to the two PWM comparators inverting inputs. Increasing error
amplifier voltage results in increased duty cycle. This increased
9
duty cycle signal is passed to the output drivers with no phase
reversal to drive the external MOSFETs. Increased duty cycle,
translating to increased ON-time for the upper MOSFET
transistor, results in increased output voltage, compensating
for the low output voltage which lead to the increase in the
error signal in the first place.
CURRENT LOOP
The current control loop is only used to finely adjust the
individual channel duty cycle, in order to balance the current
carried by each phase. The information used for this control is
the voltage that is developed across r DS(ON) of each lower
MOSFET, while they are conducting. A resistor converts and
scales the voltage across each MOSFET to a current that is
applied to the current sensing circuits within the ISL6567.
Output from these sensing circuits is averaged and used to
compute a current error signal. Each PWM channel receives a
current signal proportional to the difference between the
average sensed current and the individual channel current.
When a PWM channel’s current is greater than the average
current, the signal applied via the summing correction circuit
to the PWM comparator reduces the output pulse width (duty
cycle) of the comparator to compensate for the detected above
average current in the respective channel.
MULTI-PHASE POWER CONVERSION
Multi-phase power conversion provides a cost-effective power
solution when load currents are no longer easily supported by
single-phase converters. Although its greater complexity
FN9243.4
August 9, 2011
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