参数资料
| 型号： | ISL6569CR-T |
| 厂商： | Intersil |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6569
feeds out the OFS pin into a user selected external resistor
EXTERNAL CIRCUIT
ISL6569 INTERNAL CIRCUIT
to ground. The resulting voltage across the resistor, V OFS , is
R C
C C
COMP
FB
ERROR AMPLIFIER
-
internally divided down by ten to create the offset voltage.
This method of offsetting the DAC voltage is more accurate
than external methods of level-shifting the FB pin.
TABLE 1. VOLTAGE IDENTIFICATION CODES
R FB
+
V DROOP
IOUT
I AVG
+
+
V COMP
VID4
0
VID3
0
VID2
0
VID1
0
VID0
0
DAC
1.550
-
VDIFF
REFERENCE
VOLTAGE
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1.525
1.500
1.475
REMOTE
SENSE
V OUT
VSEN
+
0
0
0
0
1
1
0
0
0
1
1.450
1.425
POINTS
GND
RGND
-
0
0
1
1
0
1.400
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
0
0
0
1
1
0
1
0
1
0
1.375
1.350
R OFS
+
V OFS
-
OFS
x0.1
100 μ A
OFFSET
VOLTAGE
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1.325
1.300
1.275
0
1
1
0
0
1.250
FIGURE 6. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6569 features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, V DIFF , is then tied through an external
resistor to the inverting input of the error amplifier.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20 μ A pull-up to an internal 2.5V
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pull-
up current sources, but a slight accuracy error can occur if
they are pulled above 2.9V. The DAC-selected reference
voltage is connected to the non-inverting input of the error
amplifier.
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
The ISL6569 features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
11
The integrating compensation network shown in Figure 6
assures that the steady-state error in the output voltage is lim-
ited to the error in the reference voltage (output of the DAC)
plus offset errors in the OFS current source, remote-sense
and error amplifiers. Intersil specifies the guaranteed toler-
FN9085.7
December 29, 2004
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