参数资料
| 型号： | ISL6569CR-T |
| 厂商： | Intersil |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6569
MOSFETs
The choice of MOSFETs depends on the current each
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
P UP , 1 ≈ V IN ? ------ + --------- ? ? ---- 1 ? f S
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
? 2 2 ? ? 2 ?
I M I PP ? t ?
(EQ. 15)
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
The upper MOSFET begins to conduct and this transition
occurs over a time t 2 . In Equation 16, the approximate power
loss is P UP,2 .
P UP , 2 ≈ V IN ? ------ – --------- ? ? ---- 2 ? f S
MOSFET is due to current conducted through the channel
resistance (r DS(ON) ). In Equation 13, I M is the maximum
continuous output current; I PP is the peak-to-peak inductor
? I M I PP ? ? t ?
? 2 2 ? ? 2 ?
(EQ. 16)
current (see Equation 1); d is the duty cycle (V OUT /V IN ); N is
the number of active channels; and L is the per-channel
inductance.
A third component involves the lower MOSFET’s reverse-
recovery charge, Q rr . Since the inductor current has fully
? I M ? 2 I L , PP ( 1 – d )
P L = r DS ( ON ) ? ------ ? ( 1 – d ) + --------------------------------
? 2 ?
12
(EQ. 13)
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q rr , it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P UP,3 and is approximately
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
P UP , 3 ≈ V IN Q rr f S
(EQ. 17)
I PP2
? I M ?
P UP , 4 = r DS ( ON ) ? ------ ? d + ----------
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I M , V D(ON) ; the switching frequency,
f S ; and the length of dead times, t d1 and t d2 , at the
beginning and the end of the lower-MOSFET conduction
interval respectively.
Finally, the resistive part of the upper MOSFET’s dissipation
is given in Equation 18 as P UP,4 .
2
(EQ. 18)
? 2 ? 12
I PP ?
? I
P D = V D ( ON ) f S ? ------ + --------- ? t
? d1 + ? ? ------ – --------- ? ? d2
I M I PP M
? 2
2 2 2
t
(EQ. 14)
In this case, of course, r DS(ON) is the on resistance of the
upper MOSFET.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P L and P D .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q rr ; and the upper MOSFET r DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 15, 16, 17 and 18. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
and different switching frequencies until converging upon the
best solution.
Current Sensing
The ISEN pins are denoted ISEN1 and ISEN2. The resistors
connected between these pins and their respective phase
nodes determine the gain in the load-line regulation loop and
the channel-current balance loop. Select the values for these
resistors based on the room temperature r DS(ON) of the
lower MOSFETs; the full-load operating current, I FL ;
according to Equation 19 (see also Figure 4).
R ISEN = ----------------------- ) --------
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
r DS ( ON I FL
50 × 10 – 6 2
(EQ. 19)
ramps up to assume the full inductor current. In Equation 15,
16
In certain circumstances, it may be necessary to adjust the
value of one or both of the ISEN resistors. This can arise
when the components of one channel are inhibited from
dissipating their heat so that the affected channel runs hotter
than desired (see the section entitled Channel-Current
FN9085.7
December 29, 2004
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| ISL6569CRZ | 功能描述:IC REG CTRLR DIVIDER PWM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6569CRZ-T | 功能描述:IC REG CTRLR DIVIDER PWM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6571CR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intersil Corporation 功能描述: |
| ISL6571CR-T | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISL6571CRZ | 功能描述:IC MOSF DRVR/SYNC SW COMPL 68QFN RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 内部开关 系列:- 标准包装:1,000 系列:- 类型:高端/低端驱动器 输入类型:SPI 输出数:8 导通状态电阻:850 毫欧，1.6 欧姆 电流 - 输出 / 通道:205mA，410mA 电流 - 峰值输出:500mA，1A 电源电压:9 V ~ 16 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:PG-DSO-20-45 包装:带卷 (TR) |
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