参数资料
| 型号： | ISL6611AIRZ |
| 厂商： | Intersil |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DOUBLER PWM 16-QFN |
| 标准包装： | 75 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 是 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6611A
PVCC
R HI1
BOOT
G
C GD
D
C DS
this channel should remain ON to protect the system from an
overvoltage event even when the controller is disabled.
SYNC Operation
The ISL6611A can be set to interleaving mode or
synchronous mode by pulling the SYNC pin to GND or VCC,
R LO1
UGATE
R G1
R GI1
C GS
Q1
respectively. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage
S
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
droop and current balance while it still can maintain
interleaving operation at DC load conditions. However, an
excessive ringback can occur; hence, the synchronous
mode operation could have drawbacks. Figure 6 shows how
to generate a synchronous pulse only when an transient
load is applied. The comparator should be a fast comparator
with a minimum delay.
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
C DS
Q2
20k Ω
2k Ω
49.9k Ω
+
-
1.0 nF
VCC
0 Ω
1k Ω
DNP
SYNC
GND
S
COMP
FIGURE 6. TYPICAL SYNC PULSE GENERATOR
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Current Balance and Maximum Frequency
EN_PH Operation
EN_PH
PWM
UGATE
The ISL6611A utilizes r DS(ON) sensing technique to balance
both channels, while the sample and hold circuits refer to
GND pin. The phase current sensing resistors are
integrated, while the current gain can be scaled by the
impedance on the IGAIN pin, as shown in Table 1. In most
applications, the default option should just work fine.
TABLE 1. CURRENT GAIN SELECTION
IMPEDANCE TO GND
CURRENT GAIN
LGATE
FIGURE 5. TYPICAL EN_PH OPERATION TIMING DIAGRAM
The ISL6611A disables the phase doubler operation when the
OPEN
0 Ω
49.9k Ω
DEFAULT
DEFAULT/2
DEFAULT/5
EN_PH pin is pulled to ground and after it sees the PWM
falling edge. The PWM pin is pulled to VCC at the PWM falling
edge. With the PWM line pulled high, the controller will disable
the corresponding phase and the higher number phases.
When the EN_PH is pulled high, the phase doubler will pull
the PWM line to tri-state and then will be enabled at the
leading edge of PWM input. Prior to a leading edge of PWM, if
the PWM is low, both LGATEA and LGATEB remain in
tri-state unless the corresponding phase node (PHASEA,
PHASEB) is higher than 80% of VCC. This provides additional
protection if the doubler is enabled while the high-side
MOSFET is shorted. However, this feature limits the
pre-charged output voltage to less than 80% of VCC. Note
that the first doubler should always tie its EN_PH pin high
since Intersil controllers do not allow PWM1 pulled high and
11
In addition to balancing the effective UGATE pulse width of
phase A and phase B via standard r DS(ON) current sensing
technique, a fast path is also added to swap both channels’
firing order when one phase carries much higher current
than the other phase. This improves the current balance
between phase A and phase B during high frequency load
transient events.
Each phase starts to sample current 200ns (t BLANK ) after
LGATE falls and lasts for 400ns (t SAMP ) or ends at the rising
edge of PWM if the available sampling time (t AVSAMP ) is
< 400ns. The available sampling time (t AVSAMP ) depends
upon the blanking time (t BLANK ), the duty cycle (D), the
rising and falling time of low-side gate drive (t LR , t LF ), the
total propagation delay (t PD = t PDLL + t PDLU ), and the
switching frequency (F SW) . As the switching frequency and
the duty cycle increase, the available sampling time could be
FN6881.1
August 28, 2012
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