参数资料
| 型号： | ISL6611AIRZ |
| 厂商： | Intersil |
| 文件页数： | 4/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DOUBLER PWM 16-QFN |
| 标准包装： | 75 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 是 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6611A
Functional Pin Descriptions
PACKAGE
PIN
PIN #
1
2
3
4
5
6
7
SYMBOL
GND
LGATEA
PVCC
IGAIN
PGND
LGATEB
EN_PH
FUNCTION
Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the
r DS(ON) current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC.
Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on
Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits.
Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET.
Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to
VCC at the PWM falling edge and then enters tri-state.
8
9
PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin
provides a return path for the upper gate drive.
UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET.
10
11
BOOTB
BOOTA
Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin
and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap
Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin
and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
12
13
UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET.
PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin
provides a return path for the upper gate drive.
14
15
16
17
VCC
PWM
SYNC
PAD
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively
modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for
further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and
the PWM input starts transitioning low.
A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180°
out-of-phase.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
4
FN6881.1
August 28, 2012
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