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参数资料
| 型号： | ISL6754DBEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR ISL6754 |
| 标准包装： | 1 |
| 系列： | * |
ISL6754
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200μA internal current source.
The discharge duration is determined by RTD and CT.
operation. The DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. Average current limit will prevent the
instability and allow continuous operation in current limit
T C ≈ 11.5 ? 10 ? CT
3
S
(EQ. 1)
provided the control loop is designed with adequate
bandwidth.
The propagation delay from CS exceeding the current limit
T D ≈ ( 0.06 ? RTD ? CT ) + 50 ? 10
– 9
S
(EQ. 2)
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
T SW = T C + T D = ------------
1
F SW
S
(EQ. 3)
The current sense signal applied to the CS pin connects to
the peak current comparator and a sample and hold
where T C and T D are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, T SW is the
oscillator period, and F SW is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
averaging circuit. After a 70ns leading edge blanking (LEB)
delay, the current sense signal is actively sampled during the
on time, the average current for the cycle is determined, and
the result is amplified by 4x and output on the I OUT pin. If an
RC filter is placed on the CS input, its time constant should
not exceed ~50ns or significant error may be introduced on
I OUT .
T C
D = ------------
T SW
DT = 1 – D
(EQ. 4)
(EQ. 5)
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle
peak overcurrent protection which provides fast response.
The cycle-by-cycle peak current limit results in pulse-by-pulse
duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the threshold,
the active output pulse is immediately terminated. This results
in a decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6754 operates
continuously in an overcurrent condition without shutdown.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent
protection also maintains flux balance in the transformer by
maintaining duty cycle symmetry between half-cycles. If
voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
10
FIGURE 5. CS INPUT vs I OUT
Figure 5 shows the relationship between the CS signal and
I OUT under steady state conditions. I OUT is 4x the average
of CS. Figure 6 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external
sine wave. Notice I OUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
FN6754.1
September 29, 2008
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