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参数资料
| 型号： | ISL6754DBEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR ISL6754 |
| 标准包装： | 1 |
| 系列： | * |
ISL6754
maintains the current, which now circulates around the path
of switch UR, the transformer primary, and switch UL. When
switch LL opens, the output inductor current free-wheels
predominantly through diode D1. Diode D2 may actually
conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
CT
through the remainder of the half-cycle.
OUTLL
VIN+
UL
UR
D1
I S
OUTLR
I P
L L
VOUT+
OUTLLN
RTN
(SR1)
LL
LR
D2
OUTLRN
(SR2)
VIN-
FIGURE 18. UR - UL FREE-WHEELING PERIOD
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
FIGURE 20. BASIC WAVEFORM TIMING
Referring to Figure 20, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTLL/LR
off), and one or the other being off when OUTLL or OUTLR is
on. If OUTLL is on, its corresponding SR must also be on,
indicating that OUTLRN is the correct SR control signal.
Likewise, if OUTLR is on, its corresponding SR must also be
on, indicating that OUTLLN is the correct SR control signal.
UL
UR
L L
D1
I S
VOUT+
A useful feature of the ISL6754 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
I P
RTN
LR) and the their complements (OUTLLN, OUTLRN) by
±300ns. This feature allows the designer to compensate for
LL
LR
differences in the propagation times between the PWM FETs
VIN-
D2
and the SR FETs. A voltage applied to V ADJ controls the
phase relationship.
FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
CT
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L L I P2 ),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6754 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
17
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 21. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < V ADJ < 2.425V
FN6754.1
September 29, 2008
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| ISL6801ABT | 功能描述:IC DRIVER HISIDE BOOTSTRAP 8SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
| ISL6801ABTS2357 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
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