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参数资料
| 型号： | ISL6754DBEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR ISL6754 |
| 标准包装： | 1 |
| 系列： | * |
ISL6754
1 VREF
2
20
19
CT
3
4
ISL6754
18
17
DEADTIME
R9
5 CT
6
7
16
15
14
OUTLL
OUTLR
PWM
PWM
PWM
PWM
8 RAMP
13
R6
9 CS
10
12
GND 11
OUTUR
RESONANT
DELAY
R CS
C4
CT
OUTUL
RESDEL
WINDOW
FIGURE 12. BRIDGE DRIVE SIGNAL TIMING
To understand how the ZVS method operates one must
FIGURE 11. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 22
include the parasitic elements of the circuit and examine a
full switching cycle.
VIN+
and 23 require modification. Equation 22 becomes:
UL
UR
D1
V e – Δ V CS = ----------------------
2D ? R6
R6 + R9
V
(EQ. 25)
L L
VOUT+
RTN
and Equation 23 becomes:
LL
LR
( 2D – V e + Δ V CS ) ? R6
V e – Δ V CS
R9 = -------------------------------------------------------------
Ω
(EQ. 26)
VIN-
D2
FIGURE 13. IDEALIZED FULL-BRIDGE
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
The ISL6754 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
In Figure 13, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 14, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I P and I S , respectively.
VIN+
UL
UR
L L
D1
I S
VOUT+
I P
RTN
LL
LR
D2
VIN-
FIGURE 14. UL - LR POWER TRANSFER CYCLE
15
FN6754.1
September 29, 2008
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| ISL6801ABT | 功能描述:IC DRIVER HISIDE BOOTSTRAP 8SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
| ISL6801ABTS2357 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
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