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参数资料
| 型号： | ISL6754DBEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR ISL6754 |
| 标准包装： | 1 |
| 系列： | * |
ISL6754
τ resdel = -------------------- ? DT
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR which charges
the node to VIN and then forward biases the body diode of
upper switch UR.
VIN+
where τ is the resonant transition time, L L is the leakage
inductance, C P is the parasitic capacitance, and R is the
equivalent resistance in series with L L and C P .
The resonant delay is always less than or equal to the
deadtime and may be calculated using Equation 28.
V resdel
S (EQ. 28)
2
UL
UR
L L
D1
I S
VOUT+
where τ resdel is the desired resonant delay, V resdel is a
voltage between 0V and 2V applied to the RESDEL pin, and
I P
RTN
DT is the deadtime (see Equations 1 through 5).
When the upper switches toggle, the primary current that
LL
LR
was flowing through UL must find an alternate path. It
D2
VIN-
FIGURE 15. UL - UR FREE-WHEELING PERIOD
The primary leakage inductance, L L , maintains the current
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
RESDEL is set properly, switch LL will be turned on at this
time. The output inductor does not assist this transition. It is
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
VIN+
UL
UR
D1
I S
the output inductor current free-wheels through both output
L L
VOUT+
diodes, D1 and D2. During the switch transition, the output
inductor current assists the leakage inductance in charging
I P
RTN
the upper and lower bridge FET capacitance.
LL
LR
The current flow from the previous power transfer cycle
tends to be maintained during the free-wheeling period
because the transformer primary winding is essentially
shorted. Diode D1 may conduct very little or none of the
free-wheeling current, depending on circuit parasitics. This
behavior is quite different than occurs in a conventional
hard-switched full-bridge topology where the free-wheeling
current splits nearly evenly between the output diodes, and
flows not at all in the primary.
This condition persists through the remainder of the half-
cycle.
D2
VIN-
FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
purely a resonant transition driven by the leakage
inductance.
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated in Figure 17.
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
VIN+
UL
UR
L L
D1
VOUT+
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
RTN
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
LL
LR
D2
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 27.
VIN-
FIGURE 17. UR - LL POWER TRANSFER CYCLE
The UR - LL power transfer period terminates when switch
τ = --- -----------------------------------
--------------- – ----------
L L C P
π 1
2 2
1 R
2
4L L
16
(EQ. 27)
LL turns off as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to V IN and then forward biases the body diode of upper
switch UL. As before, the output inductor current assists in
this transition. The primary leakage inductance, L L ,
FN6754.1
September 29, 2008
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