参数资料
| 型号： | ISL78220ANEZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER |
| 标准包装： | 1,000 |
| 系列： | * |
ISL78220
When PWM_TRI is tied to GND (Logic LOW), the PWM outputs will
be 2-levels (i.e: 0V and 5V).When PWM_TRI is pulled to VCC
(Logic HIGH), apart from generating the 0V and 5V PWM signals,
the PWM outputs can also generate 2.5V tri-level signal. The
external driver can identify this tri-level signal and turn off both
low side and high side output signals accordingly.
The truth table regarding V MODE and V PWM_TRI for different
mode of applications is summarized in Table 1.
TABLE 1. OPERATION MODE FOR DIFFERENT APPLICATIONS
EXTERNAL
DRIVER
IDENTIFY
PWM 2.5V TRI-LEVEL
Operation Initialization Before
Soft-Start
Prior to converter initialization, proper conditions must exist on the
enable inputs (EN pin) and VCC pin. When both conditions are met,
the controller begins soft-start. Once the output voltage is within
the proper window of operation, V PGOOD is asserted logic high.
Figure 14 shows the ISL78220 internal circuit functions before
the soft-start begins.
CIRCUIT INITIALIZATION BEFORE SOFT- START
EN
CASE
A
MODE
1
_TRI
1
SIGNAL?
Yes
APPLICATIONS
Synchronous boost for audio
amplifier power supply. No
phase dropping. (Note)
0
VCC
POR
t
t
B
Analog
1
Yes
Applications that need
0
t1
t2
t3
t4
t5
THEN SOFT- START BEGINS
improving light load efficiency
(automatic phase dropping +
cycle-by-cycle diode emulation
+ pulse skipping).
0
PWM_DETECTION
t
C
1
0
No
Applications that the external
driver cannot identify tri-level
PWM
signal, no phase dropping.
0
t
D
Analog
0
No
Applications that the external
driver cannot identify tri-level
signal, with improved light load
efficiency (e.g., 6-phase
non-synchronous boost with
phase dropping).
NOTE: Forced minimum ON pulses exists.
Considerations for Audio
Amplifier Power Supply
Application
For multiphase boost converters used in audio amplifier
applications, it is preferred to have the following features:
1. Automatic phase dropping function is NOT needed because
the load is fast changing.
2. In car audio amplifier applications, the switching frequency is
preferred to be fixed, such that it will not interfere with
FM/AM band.
3. For synchronous boost, diode emulation is needed during
start-up in order to prevent negative current dumping to the
input side.
4. For synchronous boost, a maximum duty cycle limitation on
the synchronous FET is preferred.
Based on the above mentioned “preferred features”, For audio
amplifier applications, it does not need phase dropping/adding,
but it needs a tri-state PWM signal if synchronous boost structure
is used. Also in order to limit the maximum duty cycle of the
synchronous FET, the minimal turn on time of the active FET
(Low-side FET for boost structure) will be changed from fixed
130ns to variable time, which is 1/12 of the switching periods.
13
FIGURE 14. CIRCUIT INITIALIZATION BEFORE SOFT-START
As shown on Figure 14, there are 5 time intervals before the
soft-start is initialized, they are specified as t 1 , t 2 , t 3 , t 4 and t 5 ,
respectively. The descriptions for each time interval are as
follows:
Time t 1 : The enable comparator holds the ISL78220 in shutdown
until the V EN rises above 1.2V at the beginning of t 1 time period.
During t 1 , V VCC will gradually increase until it reaches the internal
power-on reset (POR) rising threshold. Then the system enters t 2 .
Time t 2 : During t 2 time, the device initialization occurs. The time
duration for t 2 is typically from 60μs to 100μs.
Time t 3 : The internal PWM detection signal will be asserted and
the system enters the t 3 period. During t 3 the ISL78220 will
detect the voltage on each PWM pin to determine the active
phase number. If PWM1 or PWM2 is accidentally pulled to VCC,
the chip will be latched off and wait for power recycling. The time
duration for t 3 is fixed to around 30μs.
Time t 4 : When internal PWM detection signal is released the
system enters t 4 period. During t 4 period the ISL78220 will wait
until the internal PLL circuits are locked to the pre-set oscillator
frequency. When PLL locking is achieved, the oscillator will
generate output at CLK_OUT pin. The time duration for t 4 is
typically around 0.5ms, depending on PLL_COMP pin
configuration.
Time t 5 : After the PLL locks the frequency, the system enters the
t 5 period. During t 5 the PWM outputs are held in a
high-impedance state (If V PWM_TRI = 1) or logic low (if
V PWM_TRI = 0), and the V DRIVE_EN is logic LOW to assure the
external drivers remain off. The ISL78220 has one unique
FN7688.3
December 24, 2013
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