参数资料
| 型号： | ISL78220ANEZ-T |
| 厂商： | Intersil |
| 文件页数： | 2/22页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER |
| 标准包装： | 1,000 |
| 系列： | * |
ISL78220
Pin Configuration
ISL78220
(44 LD 10x10 EP-TQFP)
TOP VIEW
FS
1
44 43 42 41 40 39 38 37 36 35 34
33
VIN
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
ISEN6P
ISEN6N
ISEN4P
ISEN4N
ISEN2P
ISEN2N
ISEN5P
ISEN5N
ISEN3P
PWM_INV
11 23
12 13 14 15 16 17 18 19 20 21 22
ISEN3N
Functional Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
FS
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLKOUT
PWM_INV
2
DESCRIPTION
A resistor placed from FS to ground will set the PWM switching frequency.
Use this pin to set-up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start
ramp rate and in turn determine the soft-start time.
The output of the transconductance amplifier. Place the compensation network between COMP and GND for
compensation loop design.
The inverting input of the transconductance amplifier. A resistor network should be placed between FB pin and
output rail to set the output voltage.
External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the
internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a
resistor divider network from VCC or VIN.
Bias and reference ground for the IC.
This pin programs the slope of the internal slope compensation. A resistor should be connected from SLOPE pin
to GND. Please refer to “Adjustable Slope Compensation” on page 18 for how to choose the resistor value.
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between
PLL_COMP pin and GND compensates the PLL feedback loop.
Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input
waveform. If SYNC function is not used, tie SYNC pin to GND. A 500nA current source is connected internally to
pull down the SYNC pin if it is left open.
This pin provides a clock signal to synchronize with another ISL78220. This provides scalability and flexibility. The
rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.
This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation with
inverting MOSFET drivers. Pulling this pin to VCC will invert the PWM signal for operation with non-inverting
MOSFET drivers. This function provides the flexibility for the ISL78220 to work with different drivers.
FN7688.3
December 24, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL78220ANZ-T | 制造商:Intersil Corporation 功能描述:AUTOMOTIVE GRADE 6-PHASE BOOST PWM CONTROLLER - 44LD TQFP PB - Tape and Reel |
| ISL78220EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL78220 EVALUATION BOARD 1 - 44 LEAD - TQFP - ROHS COMPLIAN - Bulk |
| ISL78223 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control |
| ISL78223AAZ | 功能描述:电流型 PWM 控制器 ZVS Full Bridge PWM Controller Adj Rect. RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL78223AAZ-T | 制造商:Intersil Corporation 功能描述:ZVS FULL BRIDGE PWM CONTROLLER, 20LD QSOP, PB-FREE W/ ANNEAL - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG CTRLR PWM ISOLATED 20QSOP 制造商:Intersil 功能描述:ZVS Full Bridge PWM- Controller Adj Rect. |
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